Turnitin
降AI改写
早检测系统
早降重系统
Turnitin-UK版
万方检测-期刊版
维普编辑部版
Grammarly检测
Paperpass检测
checkpass检测
PaperYY检测
[PDF][PDF] Collaboro: a collaborative (meta) modeling tool
Motivation Scientists increasingly rely on intelligent information systems to help them in their
daily tasks, in particular for managing research objects, like publications or datasets. The …
daily tasks, in particular for managing research objects, like publications or datasets. The …
[BUCH][B] Reasoning in Boolean Networks: logic synthesis and verification using testing techniques
W Kunz, D Stoffel - 2013 - books.google.com
Reasoning in Boolean Networks provides a detailed treatment of recent research advances
in algorithmic techniques for logic synthesis, test generation and formal verification of digital …
in algorithmic techniques for logic synthesis, test generation and formal verification of digital …
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
Tafertshofer, Ganz, Henftling - 1997 Proceedings of IEEE …, 1997 - ieeexplore.ieee.org
The paper presents a flexible and efficient approach to evaluating implications as well as
deriving indirect implications in logic circuits. Evaluation and derivation of implications are …
deriving indirect implications in logic circuits. Evaluation and derivation of implications are …
Circuit optimization by rewiring
SC Chang, LPPP Van Ginneken… - IEEE Transactions …, 1999 - ieeexplore.ieee.org
Presents a very efficient optimization method suitable for multi-level combinational circuits.
The optimization is based on incremental restructuring of a circuit through a sequence of …
The optimization is based on incremental restructuring of a circuit through a sequence of …
Fast boolean optimization by rewiring
SC Chang, LPPP van Ginneken… - … on Computer Aided …, 1996 - ieeexplore.ieee.org
This paper presents a very efficient Boolean logic optimization method. The boolean
optimization is achieved by adding and removing redundant wires in a circuit. Our algorithm …
optimization is achieved by adding and removing redundant wires in a circuit. Our algorithm …
SAT based ATPG using fast justification and propagation in the implication graph
P Tafertshofer, A Ganz - … on Computer-Aided Design. Digest of …, 1999 - ieeexplore.ieee.org
In this paper we present new methods for fast justification and propagation in the implication
graph (IG) which is the core data structure of our SAT based implication engine. As the IG …
graph (IG) which is the core data structure of our SAT based implication engine. As the IG …
[PDF][PDF] Timing driven placement in interaction with netlist transformations
G Stenz, BM Riess, B Rohfleisch… - Proceedings of the 1997 …, 1997 - dl.acm.org
In this paper, we present a new approach that performs timing driven placement for standard
cell circuits in interaction with netlist transformations. As netlist transformations are …
cell circuits in interaction with netlist transformations. As netlist transformations are …
Igraine-an implication graph-based engine for fast implication, justification, and propagation
P Tafertshofer, A Ganz… - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
Implication, justification, and propagation are three important Boolean problems that have to
be solved during many tasks in electronic design automation (EDA) for digital circuits. As …
be solved during many tasks in electronic design automation (EDA) for digital circuits. As …
[PDF][PDF] Reducing power dissipation after technology map** by structural transformations
B Rohfleisch, A Kölbl, B Wurth - Proceedings of the 33rd annual Design …, 1996 - dl.acm.org
Due to the increasing demand for low power circuits, low power dissipation has emerged as
an important optimization goal in logic synthesis. In this paper, we show that the power …
an important optimization goal in logic synthesis. In this paper, we show that the power …
Combining technology map** with post-placement resynthesis for performance optimization
A Lu, H Eisenmann, G Stenz… - … on Computer Design …, 1998 - ieeexplore.ieee.org
This paper presents an innovative two-phase approach which combines technology
map** with logic resynthesis for minimizing the post-placement delays. The main idea is …
map** with logic resynthesis for minimizing the post-placement delays. The main idea is …