Dynamic and partial reconfiguration are key differentiating capabilities of field
programmable gate arrays (FPGAs). While they have been studied extensively in academic …

Cloud providers such as Amazon and Microsoft have begun to support on-demand FPGA
acceleration in the cloud, and hardware vendors will support FPGAs in future processors. At …

Localization and map** in unknown environments becomes more difficult as the
complexity of the environment increases. With conventional techniques, the cost of …

Fine-grain reconfigurable devices suffer from the time needed to load the configuration
bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be …

With CPU scaling slowing down in today's data centers, more functionalities are being
offloaded from the CPU to auxiliary devices. One such device is the SmartNIC, which is …

Achieving high speed run-time reconfiguration is important for the adaptation of partial
reconfiguration in many applications. The reconfiguration speed that is currently available …

7. B-1 (P1) sends message to Bo (not mapped) Cache miss handled by owner P3 containing
A1 is chosen for pre-empting Ownero asks owner to undo (A1-) P3) map (A1-) P3) entry in …

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related
applications, such as smart cars and wearable devices. However, embedded devices have …

Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have
resulted in open frameworks that offer a software API and hardware interface to allow easier …

Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of
FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of …