Accelerators and coherence: An SoC perspective

D Giri, P Mantovani, LP Carloni - IEEE Micro, 2018 - ieeexplore.ieee.org
The complexity of System-on-Chip (SoC) designs continues to grow as each SoC features
an increasing variety of loosely coupled accelerators together with multiple processor cores …

Hardware Acceleration.

MA Kim, YS Shao - IEEE Micro, 2018 - computer.org
The microarchitecture of deep neural network (DNN) inference engines is currently an area
of active research in the computer architecture community. Graphics processing units …

Rapid Execution Time Estimation for Heterogeneous Memory Systems Through Differential Tracing

N Denoyelle, S Perarnau, K Iskra, B Gerofi - International Conference on …, 2022 - Springer
As the complexity of compute nodes in high-performance computing (HPC) keeps
increasing, systems equipped with heterogeneous memory devices are becoming …

Performance Analysis of Big. LITTLE System with Various Branch Prediction Schemes

FV Rodrigues, NB Guinde - Data Science: Theory, Algorithms, and …, 2021 - Springer
With the sprinting innovation in mobile technology, cell-phone processors, nowadays, are
designed and deployed to meet the demands for high performance and low-power …

[图书][B] Simulating dataflow accelerators for deep learning application in heterogeneous system

QA Hoang - 2022 - search.proquest.com
For the past few decades, deep learning has emerged as an essential discipline that
broadens the horizon of the knowledge of humankind. At its core, Deep Neural Networks …

[PDF][PDF] Connecting Palladio with multicore CPU simulators

S Graef - 2018 - core.ac.uk
Abstract In Software Engineering simulators are typically used for Software Performance
Engineering (SPE). It is important that the simulations are accurate in order to allow …

Creating a PCI express interconnect in the gem5 simulator

KP Srinivasan - 2018 - ideals.illinois.edu
In this thesis, the objective was to implement a PCI (Peripheral Component Interconnect)
Express interconnect in the gem5 architecture simulator. The interconnect was designed …