{NICA}: An infrastructure for inline acceleration of network applications

H Eran, L Zeno, M Tork, G Malka… - 2019 USENIX Annual …, 2019 - usenix.org
With rising network rates, cloud vendors increasingly deploy FPGA-based SmartNICs (F-
NICs), leveraging their inline processing capabilities to offload hypervisor networking …

Transformations of high-level synthesis codes for high-performance computing

J de Fine Licht, M Besta, S Meierhans… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Spatial computing architectures promise a major stride in performance and energy efficiency
over the traditional load/store devices currently employed in large scale computing systems …

AnyHLS: High-level synthesis with partial evaluation

MA Özkan, A Pérard-Gayot, R Membarth… - … on Computer-Aided …, 2020 - ieeexplore.ieee.org
Field programmable gate arrays (FPGAs) excel in low power and high throughput
computations, but they are challenging to program. Traditionally, developers rely on …

Hal: Hardware-assisted load balancing for energy-efficient snic-host cooperative computing

J Huang, J Lou, S Vanavasam, X Kong… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
A typical SmartNIC (SNIC) integrates a processor comprising Arm CPU and accelerators
with a conventional NIC. The processor is designed to energy-efficiently execute network …

FLOWER: A comprehensive dataflow compiler for high-level synthesis

P Amiri, A Pérard-Gayot, R Membarth… - … Conference on Field …, 2021 - ieeexplore.ieee.org
FPGAs have found their way into data centers as accelerator cards, making reconfigurable
computing more accessible for high-performance applications. At the same time, new high …

Module-per-Object: a human-driven methodology for C++-based high-level synthesis design

JS da Silva, FR Boyer… - 2019 IEEE 27th Annual …, 2019 - ieeexplore.ieee.org
High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware
design. However, achieving the highest Quality-of-Results (QoR) with HLS is still …

[HTML][HTML] An On-Chip Architectural Framework Design for Achieving High-Throughput Multi-Channel High-Bandwidth Memory Access in Field-Programmable Gate …

X Kong, Z Zhu, C Feng, Y Zhu, X Zheng - Electronics, 2025 - mdpi.com
The integration of High-Bandwidth Memory (HBM) into Field-Programmable Gate Arrays
(FPGAs) has significantly enhanced data processing capabilities. However, the …

[HTML][HTML] A highly configurable high-level synthesis functional pattern library

L Huang, T Gao, D Li, Z Wang, K Wang - Electronics, 2021 - mdpi.com
FPGA has recently played an increasingly important role in heterogeneous computing, but
Register Transfer Level design flows are not only inefficient in design, but also require …

Tecniche di data mining per stimare l'effort nei progetti software

L Pelonero - 2024 - tesidottorato.depositolegale.it
It is paramount to properly integrate effort estimation with good development practices. Effort
estimation is an open challenges, and it is performed to prevent software defects and delays …

[SÁCH][B] Declarative Programming Techniques for Hardware Synthesis of Image Processing Applications

MA Özkan - 2023 - search.proquest.com
Traditional hardware description languages (HDLs), such as VHDL and Verilog, are widely
used for designing digital electronic circuits, eg, application-specific integrated circuits …