Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection
SK Mousavikia, E Gholizadehazari… - IEEE …, 2022 - ieeexplore.ieee.org
This paper describes the design and implementation of a driver drowsiness detection (DDD)
system using a modified RiscV processor on a field-programmable gate array (FPGA). To …
system using a modified RiscV processor on a field-programmable gate array (FPGA). To …
The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension
HW Oh, SE Lee - IEEE Access, 2023 - ieeexplore.ieee.org
Edge computing is becoming increasingly popular in artificial intelligence (AI) application
development due to the benefits of local execution. One widely used approach to overcome …
development due to the benefits of local execution. One widely used approach to overcome …
RollBin: reducing code-size via loop rerolling at binary level
Code size is an increasing concern on resource constrained systems, ranging from
embedded devices to cloud servers. To address the issue, lowering memory occupancy has …
embedded devices to cloud servers. To address the issue, lowering memory occupancy has …
Evaluation of bit manipulation instructions in optimization of size and speed in RISC-V
PS Babu, S Sivaraman, DN Sarma… - … conference on VLSI …, 2021 - ieeexplore.ieee.org
With an ever-increasing usage of electronic controllers in various disciplines that could be
attributed to Industry 4.0, Internet of Things (IoT) and quick shift in computational paradigms …
attributed to Industry 4.0, Internet of Things (IoT) and quick shift in computational paradigms …
NOVLI-ISA: A Novel Optimized Variable-Length Inclusive Instruction Set Architecture for RV32I/E Architecture
A Dyab, HF Ugurdag - 2024 IEEE East-West Design & Test …, 2024 - ieeexplore.ieee.org
This paper proposes a Novel, Optimized Variable-Length Inclusive ISA for RV32I/E
architectures, namely, NOVLI-ISA. The main objective of this work is to reduce the code size …
architectures, namely, NOVLI-ISA. The main objective of this work is to reduce the code size …
B-Box: An Efficient and Configurable RISC-V Bit Manipulation IP Generator
S Sukumaran, PS Babu, TS Warrier, N Gala - International Symposium on …, 2023 - Springer
A rapid shift toward performance and energy efficient processors, combined with slower
transistor scaling has paved the way for Domain Specific Architectures (DSA) in mainstream …
transistor scaling has paved the way for Domain Specific Architectures (DSA) in mainstream …
[PDF][PDF] SSA-based Register Allocation for Compressed Machine Code
M Stemmer-Grabow - pp.ipd.kit.edu
Many RISC instruction sets include compressed instruction variants to improve code density.
Due to limited encoding space, these compressed variants are restricted, often in terms of …
Due to limited encoding space, these compressed variants are restricted, often in terms of …
[CITATION][C] Machine Learning-Driven GCC Loop Unrolling Optimization: Compiler Performance Enhancement Strategy Based on XGBoost
Z Shi, J Gao, X Guan - Journal of Circuits, Systems and Computers, 2025 - World Scientific
In contemporary compilers, the determination of the loop unrolling factor is traditionally
based on manually crafted heuristic rules. This approach heavily relies on human intuition …
based on manually crafted heuristic rules. This approach heavily relies on human intuition …