Building safety-critical real-time systems out of inexpensive, non-real-time, COTS
components is challenging. Although COTS components generally offer high performance …

In safety-critical cyber-physical systems, the usage of multicore platforms has been
hampered by problems due to interactions across cores through shared hardware. The …

In multiprocessor systems, the traffic on the bus does not solely originate from data transfers
due to data dependencies between tasks, but is also affected by memory transfers as result …

Real-time systems are reactive computer systems that must produce their reaction to a
stimulus within given time bounds. A vital verification requirement is to estimate the Worst …

Cache partitioning techniques have been proposed in the past as a solution for the cache
interference problem. Due to qualitative differences with general purpose platforms, real …

Integrating COTS components in critical real-time systems is challenging. In particular, we
show that the interference between cache activity and I/O traffic generated by COTS …

Tasks in an embedded system are scheduled either preemptively or non-preemptively. In
case of preemptive scheduling, interferences on the cache of the preempted and preempting …

Embedded control systems with hard real-time constraints require that deadlines are met at
all times or the system may malfunction with potentially catastrophic consequences …

Limited preemption scheduling has been introduced as a viable alternative to non-
preemptive and fully preemptive scheduling when reduced blocking times need to coexist …

The unpredictable worst-case timing behavior of multicore architectures has been the
biggest stumbling block for a widespread use of multicores in hard real-time systems. A …