Nanometer-Scale III-V MOSFETs

JA Del Alamo, DA Antoniadis, J Lin… - IEEE Journal of the …, 2016 - ieeexplore.ieee.org
After 50 years of Moore's Law, Si CMOS, the mainstream logic technology, is on a course of
diminishing returns. The use of new semiconductor channel materials with improved …

III–V nanowire transistors for low-power logic applications: a review and outlook

C Zhang, X Li - IEEE Transactions on Electron Devices, 2015 - ieeexplore.ieee.org
III-V semiconductors, especially InAs, have much higher electron mobilities than Si and have
been considered as promising candidates for n-channel materials for post-Si low-power …

III–V compound semiconductor transistors—from planar to nanowire structures

H Riel, LE Wernersson, M Hong, JA Del Alamo - Mrs Bulletin, 2014 - cambridge.org
Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic
device roadmap to further improve future performance increases of integrated circuits is …

III–V nanowire complementary metal–oxide semiconductor transistors monolithically integrated on Si

J Svensson, AW Dey, D Jacobsson, LE Wernersson - Nano letters, 2015 - ACS Publications
III–V semiconductors have attractive transport properties suitable for low-power, high-speed
complementary metal–oxide-semiconductor (CMOS) implementation, but major challenges …

High-frequency gate-all-around vertical InAs nanowire MOSFETs on Si substrates

S Johansson, E Memisevic… - IEEE Electron Device …, 2014 - ieeexplore.ieee.org
We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an
extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 …

Vertical InAs/InGaAs heterostructure metal–oxide–semiconductor field-effect transistors on Si

OP Kilpi, J Svensson, J Wu, AR Persson… - Nano …, 2017 - ACS Publications
III–V compound semiconductors offer a path to continue Moore's law due to their excellent
electron transport properties. One major challenge, integrating III–V's on Si, can be …

Combining axial and radial nanowire heterostructures: Radial Esaki diodes and tunnel field-effect transistors

AW Dey, J Svensson, M Ek, E Lind, C Thelander… - Nano …, 2013 - ACS Publications
The ever-growing demand on high-performance electronics has generated transistors with
very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1–4 …

A High-Frequency Transconductance Method for Characterization of High- Border Traps in III-V MOSFETs

S Johansson, M Berg, KM Persson… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-
semiconductor field-effect transistors (MOSFETs) is presented. The increase in …

High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth

X Miao, K Chabak, C Zhang, P K. Mohseni… - Nano Letters, 2015 - ACS Publications
Wafer-scale defect-free planar III–V nanowire (NW) arrays with∼ 100% yield and precisely
defined positions are realized via a patterned vapor–liquid–solid (VLS) growth method …

High frequency III–V nanowire MOSFETs

E Lind - Semiconductor Science and Technology, 2016 - iopscience.iop.org
III–V nanowire transistors are promising candidates for very high frequency electronics
applications. The improved electrostatics originating from the gate-all-around geometry …