High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule
This paper presents architecture of block-level-parallel layered decoder for irregular LDPC
code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11 …
code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11 …
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics
ASIC design of a high speed low power circuit for factorial calculation of a number is
reported in this paper. The factorial of a number can be calculated using iterative …
reported in this paper. The factorial of a number can be calculated using iterative …
Efficient design of magnitude and 2's complement comparators
Digital comparators are important arithmetic components used in digital systems to
determine if two numbers are equal, or if one number is greater or less than the other. In this …
determine if two numbers are equal, or if one number is greater or less than the other. In this …
Fast and efficient circuit topologies forfinding the maximum of n k-bit numbers
Finding the value and/or index of the maximum (or minimum) element of a set of numbers
(each with-bits) is a fundamental arithmetic operation and is needed in many applications …
(each with-bits) is a fundamental arithmetic operation and is needed in many applications …
A 167-ps 2.34-mW single-cycle 64-bit binary tree comparator with constant-delay logic in 65-nm CMOS
A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in
a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino …
a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino …
Design of High‐Speed Adders for Efficient Digital Design Blocks
D Yagain, A Baliga - International Scholarly Research Notices, 2012 - Wiley Online Library
The core of every microprocessor and digital signal processor is its data path. The heart of
data‐path and addressing units in turn are arithmetic units which include adders. Parallel …
data‐path and addressing units in turn are arithmetic units which include adders. Parallel …
FPGA implementation of hybrid Han-Carlson adder
S Gedam, P Zode, P Zode - 2014 2nd International Conference …, 2014 - ieeexplore.ieee.org
In this paper a modified parallel prefix adder, Hybrid Han-Carlson adder is proposed which
uses different stages of Brent-Kung and Kogge-Stone adders. Binary addition is one of the …
uses different stages of Brent-Kung and Kogge-Stone adders. Binary addition is one of the …
[PDF][PDF] Implementation of low power high speed adder's using GDI logic
AP Ramesh - Int. J. Innov. Technol. Explor. Eng, 2019 - researchgate.net
Addition is a vital arithmetic operation and is the base of other arithmetic operations such as
multiplication, subtraction and division. Adder is a digital circuit that does addition of binary …
multiplication, subtraction and division. Adder is a digital circuit that does addition of binary …
Area-efficient AdderNet hardware accelerator with merged adder tree structure
G Seo, S Ryu - IEICE Electronics Express, 2023 - jstage.jst.go.jp
This brief introduces an area-efficient AdderNet hardware accelerator. AdderNet replaces
multiply-accumulate computations of neural network processing with addition operations …
multiply-accumulate computations of neural network processing with addition operations …
[PDF][PDF] Designing an on-line magnitude comparator for higher-radix
MS Chakraborty - Int J Inf Technol Electr Eng, 2020 - iteejournal.org
On-line arithmetic attracts the computer arithmetic community primarily owing to its ability to
admit digit-level pipelining of several operations, apparently having distinct computational …
admit digit-level pipelining of several operations, apparently having distinct computational …