Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits
A new voltage mode design is presented for quaternary logic using CNTFETs. This
architecture with presentation of a new structure for voltage division can be applied on any …
architecture with presentation of a new structure for voltage division can be applied on any …
[HTML][HTML] Performance evaluation of efficient XOR structures in quantum-dot cellular automata (QCA)
MR Beigh, M Mustafa, F Ahmad - 2013 - scirp.org
Quantum-dot cellular automaton (QCA) is an emerging, promising, future generation
nanoelectronic computational architecture that encodes binary information as electronic …
nanoelectronic computational architecture that encodes binary information as electronic …
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM
AS Vidhyadharan, S Vidhyadharan - Microelectronics Journal, 2021 - Elsevier
This paper presents a CNTFET based ultra-low-power ternary SRAM design which
consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as …
consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as …
Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders
HT Tari, AD Zarandi, MR Reshadinezhad - Microelectronic Engineering, 2019 - Elsevier
Abstract Carbon Nanotube Field Effect Transistor (CNTFET) s are applied instead of silicon
transistors to conquer the constraint of MOSFETs in nano-scale, with improving the power …
transistors to conquer the constraint of MOSFETs in nano-scale, with improving the power …
Carbon nano tube field effect transistors based ternary Ex-OR and Ex-NOR gates
K Patcha, S Musala, K Vijayavardhan… - Current …, 2016 - ingentaconnect.com
Background: A carbon nanotube field-effect transistor (CNTFET) is, however a field-effect
transistor itself, which utilizes a single carbon nanotube or a multiple of carbon nanotubes …
transistor itself, which utilizes a single carbon nanotube or a multiple of carbon nanotubes …
A Novel Low Power and High Speed 9-Transistors Dynamic Full-Adder Cell Simulation and Design
P Rahimi, M Tabany… - 2023 IEEE Symposium on …, 2023 - ieeexplore.ieee.org
In this paper, a novel Full-Adder cell, named pseudo dynamic has been proposed and
designed through an intensive simulation. The circuit has only 9 transistors and no internal …
designed through an intensive simulation. The circuit has only 9 transistors and no internal …
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4≤ m≤ 10) compressors
Compressors play an important role for partial products reduction in the multiplication
process. This paper presents a new implementation for the second phase of a 16× 16-bit …
process. This paper presents a new implementation for the second phase of a 16× 16-bit …
A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications
In this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is
implemented based on multi-threshold NAND and NOR gates and transmission gate …
implemented based on multi-threshold NAND and NOR gates and transmission gate …
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders
A new hardware-friendly mathematical method for realizing low-complexity universal Adder
cells as well as its efficient hardware implementations is proposed in this paper. This method …
cells as well as its efficient hardware implementations is proposed in this paper. This method …
A low-power high-speed hybrid multi-threshold full adder design in CNFET technology
In this paper, a low-power high-speed hybrid full adder cell is proposed, which is
implemented based on two-input multi-threshold (V _ t)(V t) XNOR circuit and transmission …
implemented based on two-input multi-threshold (V _ t)(V t) XNOR circuit and transmission …