Cell circuit and layout with linear finfet structures
ST Becker - US Patent 9,563,733, 2017 - Google Patents
(57) ABSTRACT A cell circuit and corresponding layout is disclosed to include linear-
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
Finfet transistor circuit
ST Becker, MC Smayling, D Gandhi, J Mali… - US Patent …, 2014 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate …
ST Becker, MC Smayling - US Patent 7,923,757, 2011 - Google Patents
(57) ABSTRACT A restricted layout region includes a diffusion level layout including p-type
and n-type diffusion region layout shapes separated by a central inactive region. The …
and n-type diffusion region layout shapes separated by a central inactive region. The …
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions
ST Becker, MC Smayling - US Patent 7,906,801, 2011 - Google Patents
(57) ABSTRACT A restricted layout region is defined to include a diffusion level layout that
includes a plurality of diffusion region layout shapes to be formed within a portion of a …
includes a plurality of diffusion region layout shapes to be formed within a portion of a …
Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment
ST Becker, MC Smayling - US Patent 7,910,958, 2011 - Google Patents
(57) ABSTRACT A semiconductor device is disclosed as having a substrate portion that
includes a plurality of diffusion regions that include at least one p-type diffusion region and …
includes a plurality of diffusion regions that include at least one p-type diffusion region and …
Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions
ST Becker, MC Smayling - US Patent 7,932,544, 2011 - Google Patents
(57) ABSTRACT A restricted layout region in a layout of a semiconductor device is disclosed
to include a diffusion level layout includ ing a plurality of diffusion region layout shapes. The …
to include a diffusion level layout includ ing a plurality of diffusion region layout shapes. The …
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End …
ST Becker, MC Smayling - US Patent App. 12/572,077, 2010 - Google Patents
(57) ABSTRACT A cell layout of a semiconductor device includes a diffusion level layout
including a plurality of diffusion region layout shapes. The cell layout also includes a gate …
including a plurality of diffusion region layout shapes. The cell layout also includes a gate …
Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
ST Becker, MC Smayling - US Patent 7,943,967, 2011 - Google Patents
(57) ABSTRACT A semiconductor device includes a Substrate portion having a plurality of
diffusion regions defined therein. The plurality of diffusion regions are separated from each …
diffusion regions defined therein. The plurality of diffusion regions are separated from each …
Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts
ST Becker, MC Smayling - US Patent 8,258,547, 2012 - Google Patents
(57) ABSTRACT A restricted layout region includes a diffusion level layout including a
number of diffusion region layout shapes that de? ne at least one p-type diffusion region and …
number of diffusion region layout shapes that de? ne at least one p-type diffusion region and …
Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing …
ST Becker, MC Smayling - US Patent 7,932,545, 2011 - Google Patents
A semiconductor device is disclosed as having a substrate portion that includes a plurality of
diffusion regions that include at least one p-type diffusion region and at least one n-type …
diffusion regions that include at least one p-type diffusion region and at least one n-type …