Cluster-based channel assignment in multi-radio multi-channel wireless mesh networks
A Naveed, SS Kanhere - 2009 IEEE 34th Conference on Local …, 2009 - ieeexplore.ieee.org
In a typical wireless mesh network (WMN), the interfering links can broadly be classified as
coordinated and non-coordinated links, depending upon the geometric relationship. It is …
coordinated and non-coordinated links, depending upon the geometric relationship. It is …
Skybridge-3D-CMOS: A fine-grained 3D CMOS integrated circuit technology
Parallel and monolithic three-dimensional (3-D) integration directions realize 3-D integrated
circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being …
circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being …
New thermal management approach for transistor-level 3-D integtration
Among various 3-D integration approaches for beyond 2-D CMOS logic, transistor based 3-
D integrations such as monolithic 3-D [1], Skybridge [2], vertical Si nanowire CMOS [3], and …
D integrations such as monolithic 3-D [1], Skybridge [2], vertical Si nanowire CMOS [3], and …
Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS
Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect
bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC …
bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC …
Skybridge-3D-CMOS: A vertically-composed fine-grained 3D CMOS integrated circuit technology
Parallel and monolithic 3D-integration directions offer pathways to realize 3D integrated
circuits but still lead to layer-by-layer implementations. This mindset causes challenging …
circuits but still lead to layer-by-layer implementations. This mindset causes challenging …
Thermal management challenges and mitigation techniques for transistor-level 3-D integration
For beyond 2-D CMOS logic, transistor-level 3-D integrations such as monolithic 3-D [1],
Skybridge [2], SN3D [3] hold the most promise. However, such 3-D architectures within small …
Skybridge [2], SN3D [3] hold the most promise. However, such 3-D architectures within small …
Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric
At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to
fundamental device scaling limitations, interconnection overhead and complex …
fundamental device scaling limitations, interconnection overhead and complex …
Relaxation of self-heating-effect for stacked-nanowire FET and p/n-stacked 6T-SRAM layout
In this paper, we investigated the source/drain recessed contact structure to mitigate the self-
heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of …
heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of …
New 3-D CMOS fabric with stacked horizontal nanowires
As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and
interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a …
interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a …
Fine-grained 3-D integrated circuit fabric using vertical nanowires
Continuous scaling of CMOS to sub-20nm technologies is proving to be challenging as
MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC …
MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC …