Photonic crystal flip-flops: recent developments in all optical memory components

Y Pugachov, M Gulitski, D Malka - Materials, 2023 - mdpi.com
This paper reviews recent advancements in all-optical memory components, particularly
focusing on various types of all-optical flip-flops (FFs) based on photonic crystal (PC) …

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

A Morgenshtein, A Fish… - IEEE transactions on very …, 2002 - ieeexplore.ieee.org
Gate diffusion input (GDI)-a new technique of low-power digital combinatorial circuit design-
is described. This technique allows reducing power consumption, propagation delay, and …

Theory and implementation of an analog-to-information converter using random demodulation

JN Laska, S Kirolos, MF Duarte… - … on Circuits and …, 2007 - ieeexplore.ieee.org
The new theory of compressive sensing enables direct analog-to-information conversion of
compressible signals at sub-Nyquist acquisition rates. We develop new theory, algorithms …

Improved sense-amplifier-based flip-flop: Design and measurements

B Nikolic, VG Oklobdzija, V Stojanovic… - IEEE Journal of Solid …, 2000 - ieeexplore.ieee.org
Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is
presented. It was found that the main speed bottleneck of existing SAFF's is the cross …

Sense amplifier based flip-flop

R Ahmadi - US Patent 7,692,466, 2010 - Google Patents
A circuit includes an input stage, an output stage, and a delay stage. The input stage is
operative to receive a clock signal and a first and second input signal. The output stage is …

High-performance and low-power conditional discharge flip-flop

P Zhao, TK Darwish… - IEEE transactions on very …, 2004 - ieeexplore.ieee.org
In this paper, high-performance flip-flops are analyzed and classified into two categories: the
conditional precharge and the conditional capture technologies. This classification is based …

Conditional-capture flip-flop for statistical power reduction

BS Kong, SS Kim, YH Jun - IEEE Journal of Solid-State Circuits, 2001 - ieeexplore.ieee.org
This paper describes a family of novel low-power flip-flops, collectively called conditional-
capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant …

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

MS Hrishikesh, D Burger, NP Jouppi… - ACM SIGARCH …, 2002 - dl.acm.org
Microprocessor clock frequency has improved by nearly 40% annually over the past decade.
This improvement has been provided, in equal measure, by smaller technologies and …

[BUCH][B] Digital system clocking: high-performance and low-power aspects

VG Oklobdzija, VM Stojanovic, DM Markovic… - 2003 - books.google.com
Provides the only up-to-date source on the most recent advances in this often complex and
fascinating topic. The only book to be entirely devoted to clocking Clocking has become one …

Analysis and design of low-energy flip-flops

D Markovic, B Nikolic, R Brodersen - Proceedings of the 2001 …, 2001 - dl.acm.org
This paper develops a methodology for selecting and optimizing flip-flops for low-energy
systems with constant throughput. Characterization metrics, relevant to low-energy systems …