5.432, 785 A 7, 1995 Ahmed et al. 5,764,740 A 6, 1998 Holender 5,991.308 A 11/1999
Fuhrmann et al. 6,003,029 A 12/1999 Agrawal et al. 6,249,902 B1 6/2001 Igusa et al …

GO6F 3/40(2006.01) f lan for a N k on Chi C 1 h GO6F 5/78 (2006.01) oor plan for a Network
on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non …

Systems and methods described herein are directed to streaming bridge design
implementations that help intercon nect and transfer transaction packets between multiple …

7,590,959 B2 9/2009 Tanaka Q(') 7,725,859 B1* 5/2010 Lenahan et a1............... 716/119
H03K 17/00(2006-01) 7,808,968 B1* 10/2010 Kalmanek et a1.. 370/351 H04Q …

(56) References Cited 2013/0103369 A1 4/2013 Huynh et al. 2013, O151215 A1 6/2013
Mustapha US PATENT DOCUMENTS 2013, 0159944 A1 6, 2013 Uno et al. 2013, 0174113 …

8.492. 886 8,541,819 8,543,964 8,601.423 8,635,577 8,667,439 8,717,875 2002fOO71392
2002fOO73380 2002fO095430 2004/0216072 2005, 0147081 2006.0161875 2007/01 …

Addition, search, and performance of other allied activities relating to keys are performed in
a hardware hash table. Further, high performance and efficient design may be pro vided for …

Example implementations described herein are directed to a configurable building block,
such as a router, for implemen tation of a Network on Chip (NoC). The router is param …

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …

US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or performance -
Google Patents US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or …