Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
HF Ko, N Nicolici - … Transactions on Computer-Aided Design of …, 2009 - ieeexplore.ieee.org
To locate and correct design errors that escape pre-silicon verification, silicon debug has
become a necessary step in the implementation flow of digital integrated circuits. Embedded …
become a necessary step in the implementation flow of digital integrated circuits. Embedded …
Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Distributed embedded logic analysis for post-silicon validation of SOCs
HF Ko, AB Kinsman, N Nicolici - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-
time observability of the circuit's internal nodes. In this paper, we introduce a novel design …
time observability of the circuit's internal nodes. In this paper, we introduce a novel design …
Design-for-debug for post-silicon validation: Can high-level descriptions help?
N Nicolici, HF Ko - 2009 IEEE International High Level Design …, 2009 - ieeexplore.ieee.org
Post-silicon validation is an essential step in the design flow, which is needed to
demonstrate that the implemented circuit meets its intended behavior. Due to lack of in …
demonstrate that the implemented circuit meets its intended behavior. Due to lack of in …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Framework for instruction-level tracing and analysis of program executions
S Bhansali, WK Chen, S De Jong, A Edwards… - Proceedings of the 2nd …, 2006 - dl.acm.org
Program execution traces provide the most intimate details of a program's dynamic behavior.
They can be used for program optimization, failure diagnosis, collecting software metrics like …
They can be used for program optimization, failure diagnosis, collecting software metrics like …
Fast lossless compression of scientific floating-point data
P Ratanaworabhan, J Ke… - … Conference (DCC'06), 2006 - ieeexplore.ieee.org
In scientific computing environments, large amounts of floating-point data often need to be
transferred between computers as well as to and from storage devices. Compression can …
transferred between computers as well as to and from storage devices. Compression can …
Characterizing storage workloads with counter stacks
Existing techniques for identifying working set sizes based on miss ratio curves (MRCs)
have large memory overheads which make them impractical for storage workloads. We …
have large memory overheads which make them impractical for storage workloads. We …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …