Uniaxial-process-induced strained-Si: Extending the CMOS roadmap
SE Thompson, G Sun, YS Choi… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
This paper reviews the history of strained-silicon and the adoption of uniaxial-process-
induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date …
induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date …
Method for making a semiconductor device with strain enhancement
D Zhang, BY Nguyen, VY Thean, Y Shiho… - US Patent …, 2007 - Google Patents
US7282415B2 - Method for making a semiconductor device with strain enhancement - Google
Patents US7282415B2 - Method for making a semiconductor device with strain enhancement …
Patents US7282415B2 - Method for making a semiconductor device with strain enhancement …
Carrier-transport-enhanced channel CMOS for improved power consumption and performance
An effective way to reduce supply voltage and resulting power consumption without losing
the circuit performance of CMOS is to use CMOS structures using high carrier …
the circuit performance of CMOS is to use CMOS structures using high carrier …
Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing
PR Chidambaram, C Bowen… - … on Electron Devices, 2006 - ieeexplore.ieee.org
Semiconductor industry has increasingly resorted to strain as a means of realizing the
required node-to-node transistor performance improvements. Straining silicon …
required node-to-node transistor performance improvements. Straining silicon …
[KSIĄŻKA][B] Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy
JD Cressler, S Monfray, G Freeman, D Friedman… - 2018 - taylorfrancis.com
An extraordinary combination of material science, manufacturing processes, and innovative
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …
Anomalous piezoresistance effect in ultrastrained silicon nanowires
A Lugstein, M Steinmair, A Steiger, H Kosina… - Nano …, 2010 - ACS Publications
In this paper we demonstrate that under ultrahigh strain conditions p-type single crystal
silicon nanowires possess an anomalous piezoresistance effect. The measurements were …
silicon nanowires possess an anomalous piezoresistance effect. The measurements were …
Physics of hole transport in strained silicon MOSFET inversion layers
A comprehensive quantum anisotropic transport model for holes was used to study silicon
PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of …
PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of …
Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions
YC Yeo - Semiconductor science and technology, 2006 - iopscience.iop.org
We explore several technology options for the enhancement of electron and hole mobility in
complementary metal–oxide–semiconductor (CMOS) field-effect transistors, focusing on …
complementary metal–oxide–semiconductor (CMOS) field-effect transistors, focusing on …
Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High (1.5 GPa) Channel Stress
S Suthram, JC Ziegert, T Nishida… - IEEE electron device …, 2006 - ieeexplore.ieee.org
A flexure-based four-point mechanical wafer bending setup is used to apply large uniaxial
tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to~ 700 MPa of process …
tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to~ 700 MPa of process …
Mobility enhancement
This article is targeted as an introduction to the physics of strained Si and the current state of
the art in uniaxial strained Si MOSFET. The first part of the article explains how strain alters …
the art in uniaxial strained Si MOSFET. The first part of the article explains how strain alters …