[LIBRO][B] Introduction to Asynchronous Circuit Design.

J Sparsø - 2020 - orbit.dtu.dk
This book is an introduction to the design of asynchronous circuits. It is an updated and
significantly extended version of an eight-chapter tutorial that first appeared as Part I in the …

Model-checking synthesizable systemverilog descriptions of asynchronous circuits

A Bouzafour, M Renaudin, H Garavel… - 2018 24th IEEE …, 2018 - ieeexplore.ieee.org
Asynchronous circuits have key advantages in terms of low energy consumption,
robustness, and security. However, the absence of a global clock makes the design prone to …

Tiempo asynchronous circuits system verilog modeling language

M Renaudin, A Fonkoua - 2012 IEEE 18th International …, 2012 - ieeexplore.ieee.org
This paper describes the System Verilog modeling language developed by Tiempo to
design asynchronous circuits. The language enables designers to model, verify and debug …

Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection

L Lu, M Pan, Y Lu, X Li - IEEE Transactions on Computer-Aided …, 2024 - ieeexplore.ieee.org
Specifying channel-based asynchronous circuits in SystemVerilog is a promising alternative
design paradigm to combine the advantages of asynchronous circuits and industrial EDA …

Behavioral Simulation of Relative Timed Asynchronous Circuits

S Kolluru, KS Stevens - … on Very Large Scale Integration (VLSI …, 2024 - ieeexplore.ieee.org
Relative Timed design represents timing constraints in an integrated circuit as mathematical
equations. This differs from current state of the art integrated circuit design methodologies …

Observability conditions and automatic operand-isolation in high-throughput asynchronous pipelines

A Saifhashemi, PA Beerel - Integrated Circuit and System Design. Power …, 2013 - Springer
In this paper, we model conditional communication primitives of asynchronous circuits as
three-valued logic operators and adopt the theory of observability don't cares to create a …

Power optimization of asynchronous pipelines using conditioning and reconditioning based on a three-valued logic model

A Saifhashemi - 2012 - search.proquest.com
Asynchronous circuit design has long been considered a suitable alternative to synchronous
design due to its potential for achieving lower power consumption, higher robustness to …

Adding conditionality to resilient bundled-data designs

D Hand, A Katrin, W Koven - 2016 22nd IEEE International …, 2016 - ieeexplore.ieee.org
We describe a practical method of generating production ready timing violation resilient
asynchronous circuits with conditional communication from a high level hardware …

A chaotic UWB system for home networks

K Lee, S Kyeong, J Kim, Y Kim… - … Conference on Hybrid …, 2006 - ieeexplore.ieee.org
Emerging wireless technologies will play an important role in home network applications.
Chaotic UWB technology has several inherent properties that are suited to home networks …

Reconditioning: a framework for automatic power optimization of QDI circuits

A Saifhashemi, HH Huang… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper introduces reconditioning: a novel systematic technique for reducing
unnecessary power consumption of asynchronous gate-level netlists, which involves the …