This article reviews the effects of applied bias and temperature on Si/SiO 2 interface-trap
buildup and annealing rates. Electrical and spectroscopic methods are described to …

Gate dielectric damage caused by both internal and external stresses is becoming worse
because of aggressive complementary metal–oxide–semiconductor (CMOS) scaling …

Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full {VG,
VD} bias space is a challenging task. Therefore, studies usually focus on individual …

Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET
and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p-to …

Bias temperature instability (BTI) and hot-carrier degradation (HCD) are among the most
important reliability issues but are typically studied independently in an idealized setting …

An on-chip immune system against hot-carrier stress, bias temperature instability, and total
ionizing dose degradation is presented. A system on microheater provides defect annealing …

A compact hot-carrier degradation (HCD) time kinetics model is proposed for conventional,
lightly doped drain, and drain extended MOSFETs and FinFETs. It can predict measured …

In this paper, we examine the interplay of two serious reliability issues in MOSFET devices,
namely, bias temperature instability (BTI) and hot-carrier degradation (HCD). Most …

An on-the-fly self-healing device is experimentally demonstrated for sustainability of space
electronics. A high temperature, which is generated by Joule heating in a gate electrode …

The reliability and durability of integrated circuits (ICs), present in almost every electronic
system, from consumer electronics to the automotive or aerospace industries, have been …