The complexity of hardware designs has increased over the years due to the rapid
advancement of technology coupled with the need to support diverse and complex features …

Using machine learning to solve combinatorial optimization (CO) problems is challenging,
especially when the data is unlabeled. This work proposes an unsupervised learning …

An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …

While research has shown that the agile chip design methodology is promising to sustain
the scaling of computing performance in a more efficient way, it is still of limited usage in …

Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …

With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …

Functional coverage closure is an important but RTL simulation intensive aspect of
constrained random verification. To reduce these computational demands, we propose test …

Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …

Proof decomposition via assume-guarantee with helper properties, ie helpers, is one of the
most promising approaches to address the complexity of hardware formal verification (FV) …

Information-rich relational graphs have shown great potential in designing effective
representations of code for program-understanding tasks. However, the wealth of structural …