An exponential rise in transistor count, have increased the power consumption of the
modern digital system. Moreover, at lower technology node, the performance of …

This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell
with low energy consumption and high read stability, write ability, and hold stability yields in …

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and
analysis to meet the nano-regime challenges for CMOS devices and emerging devices …

Low voltage operation of digital circuits continues to be an attractive option for aggressive
power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion …

Variation in illumination conditions caused by weather, time of day, etc., makes the task
difficult when building video surveillance systems of real world scenes. Especially, cast …

The advent of the memristor breaks the scaling limitations of MOS technology and prevails
over emerging semiconductor devices. In this paper, various memristor models including …

This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-
16T) to provide complete resilience to single event upsets (SEU). The proposed cell is …

Static Random Access Memory (SRAM) is primarily used as a memory storage element,
which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust …

The implementation of the six-transistor (6T) static random access memory cell in deep
submicrometer region has become difficult due to the compromise between area, power …

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event
Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge …