Recent progress in quantum photonic chips for quantum communication and internet

W Luo, L Cao, Y Shi, L Wan, H Zhang, S Li… - Light: Science & …, 2023 - nature.com
Recent years have witnessed significant progress in quantum communication and quantum
internet with the emerging quantum photonic chips, whose characteristics of scalability …

The future of computing beyond Moore's Law

J Shalf - Philosophical Transactions of the Royal Society …, 2020 - royalsocietypublishing.org
Moore's Law is a techno-economic model that has enabled the information technology
industry to double the performance and functionality of digital electronics roughly every 2 …

Integrated photonics packaging: challenges and opportunities

L Ranno, P Gupta, K Gradkowski, R Bernson… - ACS …, 2022 - ACS Publications
Packaging of photonic integrated circuit (PIC) chips is an essential and critical step before
they can be integrated into functional optoelectronic systems. Photonic packaging is …

Peta-scale embedded photonics architecture for distributed deep learning applications

Z Wu, LY Dai, A Novick, M Glick, Z Zhu… - Journal of Lightwave …, 2023 - ieeexplore.ieee.org
As Deep Learning (DL) models grow larger and more complex, training jobs are
increasingly distributed across multiple Computing Units (CU) such as GPUs and TPUs …

Glass platform for co-packaged optics

L Brusberg, JR Grenier, AR Zakharian… - IEEE Journal of …, 2023 - ieeexplore.ieee.org
Placing the electrical and photonic chiplets in a single package leads to significant power
reduction. Chiplets are connected by fine-line electrical routing over a length of a few …

PolarFly: a cost-effective and flexible low-diameter topology

K Lakhotia, M Besta, L Monroe, K Isham… - … Conference for High …, 2022 - ieeexplore.ieee.org
In this paper we present PolarFly, a diameter-2 network topology based on the Erdos-Renyi
family of polarity graphs from finite geometry. This is the first known diameter-2 topology that …

Research toward wafer-scale 3D integration of InP membrane photonics with InP electronics

S Abdi, V Nodjiadjim, R Hersent, M Riet… - IEEE Transactions …, 2024 - ieeexplore.ieee.org
In this study, we focus on the development of key processes towards wafer-scale 3-
dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP …

Constructal design for the layout of multi-chip module based on thermal-flow-stress coupling calculation

G Nan, Z **e, X Guan, X Ji, D Lin - Microelectronics Reliability, 2021 - Elsevier
The thermal-flow-stress coupling model of multi-chip module with uniform heat generation
under natural convection condition is established. Taking the chip aspect ratio and edge …

Efficient intra-rack resource disaggregation for HPC using co-packaged DWDM photonics

G Michelogiannakis, Y Arafa, B Cook… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
The diversity of workload requirements and increasing hardware heterogeneity in emerging
high performance computing (HPC) systems motivate resource disaggregation. Resource …

PINE: photonic integrated networked energy efficient datacenters (ENLITENED program)

M Glick, NC Abrams, Q Cheng, MY Teh… - Journal of Optical …, 2020 - opg.optica.org
We review the motivation, goals, and achievements of the Photonic Integrated Networked
Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects …