Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
BD Briggs, CB Peethala, DL Rath, J Lee… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal
pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to …
pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to …
Method for manufacturing fully aligned via structures having relaxed gapfills
The present disclosure generally relates to semiconductor structures and, more particularly,
to fully aligned via struc tures having relaxed gapfills and methods of manufacture. The …
to fully aligned via struc tures having relaxed gapfills and methods of manufacture. The …
Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme
JS Chawla, RA Brain, RE Schenker, KJ Singh… - US Patent …, 2018 - Google Patents
Interconnect structures having alternating dielectric caps and an etchstop liner for
semiconductor devices and methods for manufacturing such devices are described …
semiconductor devices and methods for manufacturing such devices are described …
Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)
JJ Xu, JJ Zhu, C fei Yeap - US Patent 10,354,912, 2019 - Google Patents
Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for
integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an …
integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an …
Structure and method to improve FAV RIE process margin and electromigration
BD Briggs, J Lee, TE Standaert - US Patent 9,953,865, 2018 - Google Patents
A method of forming fully aligned vias in a semiconductor device includes forming an Mx
level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level …
level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level …
Semiconductor device including via plug and method of forming the same
EB Lee, JM Baek, SH Ahn, HS Oh - US Patent 10,461,027, 2019 - Google Patents
A semiconductor device includes a lower insulating layer disposed on a substrate. A
conductive pattern is formed in the lower insulating layer. A middle insulating layer is …
conductive pattern is formed in the lower insulating layer. A middle insulating layer is …
Selective and non-selective barrier layer wet removal
A method for manufacturing a semiconductor device includes forming a dielectric layer on a
substrate, forming a plurality of openings in the dielectric layer, conformally depositing a …
substrate, forming a plurality of openings in the dielectric layer, conformally depositing a …
Via prefill in a fully aligned via
L Zhao, A Kolics, Y Dordi - US Patent App. 15/986,661, 2019 - Google Patents
An electrically conductive structure in an integrated circuit (IC) includes a bottom metal line
and a top metal line with via providing electrical interconnection between the bottom metal …
and a top metal line with via providing electrical interconnection between the bottom metal …
Fully aligned via with integrated air gaps
A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer
interconnects arrayed across the dielectric layer with the second metallization layer …
interconnects arrayed across the dielectric layer with the second metallization layer …
Methods of producing fully self-aligned vias and contacts
Y Zhang, R Freed, NK Ingle, HY Hwang… - US Patent …, 2020 - Google Patents
Methods and apparatus to form fully self-aligned vias are described. First conductive lines
are recessed in a first insulating layer on a substrate. A first metal film is formed in the …
are recessed in a first insulating layer on a substrate. A first metal film is formed in the …