Structure and method for a high-performance electronic packaging assembly
KY Ahn, L Forbes, EH Cloud - US Patent 6,570,248, 2003 - Google Patents
3,923,567 A 12/1975 Lawrence...................... 156/7(57) ABSTRACT 3'959'O47 A 5/1976
Alberts et a1 ' 156/8 An improved structure and method are provided for increas 3,982,268 A …
Alberts et a1 ' 156/8 An improved structure and method are provided for increas 3,982,268 A …
Progress in low-power switched optical interconnects
Optical links have successfully displaced electrical links when their aggregated bandwidth-
distance product exceeds~ 100 Gb/sm because their link energy per bit per unit distance is …
distance product exceeds~ 100 Gb/sm because their link energy per bit per unit distance is …
Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap
Technologies now exist for implementing dense surface-normal optical interconnections for
silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining …
silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining …
Structure and method for a high performance electronic packaging assembly
KY Ahn, L Forbes, EH Cloud - US Patent 6,281,042, 2001 - Google Patents
An improved structure and method are provided for increasing the operational bandwidth
between different circuit devices, eg logic and memory chips, without requiring changes in …
between different circuit devices, eg logic and memory chips, without requiring changes in …
Optoelectronic-VLSI: Photonics integrated with VLSI circuits
Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic
devices with silicon VLSI electronics. We review the motivations and status of emerging OE …
devices with silicon VLSI electronics. We review the motivations and status of emerging OE …
Silicon interposer with optical connections
KY Ahn, L Forbes - US Patent 6,821,802, 2004 - Google Patents
395047 A 5/1976 Alberts et al.......... 156/8 one, or a number of, Semiconductor chips located
on oppos 3,982.268 A 9/1976 Anthony et al........ 357/55 ing Surfaces of the Silicon …
on oppos 3,982.268 A 9/1976 Anthony et al........ 357/55 ing Surfaces of the Silicon …
Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
KY Ahn, L Forbes - US Patent 6,379,982, 2002 - Google Patents
(57) ABSTRACT A Semiconductor device wafer-on-Support wafer package comprising a
plurality of Segmentable chip-Scale packages and method of constructing, burning-in, and …
plurality of Segmentable chip-Scale packages and method of constructing, burning-in, and …
Compact system module with built-in thermoelectric cooling
KY Ahn, L Forbes, EH Cloud - US Patent 7,022,553, 2006 - Google Patents
HOIL 2/302(2006.01) An improved integrated circuit package for providing built HOIL
23/34(2006.01) in heating or cooling to a semiconductor chip is provided. HOIL …
23/34(2006.01) in heating or cooling to a semiconductor chip is provided. HOIL …
3-D integration of MQW modulators over active submicron CMOS circuits: 375 Mb/s transimpedance receiver-transmitter circuit
We accomplish the integration of GaAs-AlGaAs multiple quantum well modulators directly on
top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved …
top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved …
Performance Comparisons Between Cu/Low-, Carbon-Nanotube, and Optics for Future On-Chip Interconnects
H Cho, KH Koo, P Kapur… - IEEE Electron Device …, 2007 - ieeexplore.ieee.org
In this letter, we compare the performance of carbon nanotubes and optical interconnects
with the scaled Cu/Iow-kappa interconnects for future high-performance integrated circuits …
with the scaled Cu/Iow-kappa interconnects for future high-performance integrated circuits …