A survey and evaluation of FPGA high-level synthesis tools
High-level synthesis (HLS) is increasingly popular for the design of high-performance and
energy-efficient heterogeneous systems, shortening time-to-market and addressing today's …
energy-efficient heterogeneous systems, shortening time-to-market and addressing today's …
High-performance accurate and approximate multipliers for FPGA-based hardware accelerators
Multiplication is one of the widely used arithmetic operations in a variety of applications,
such as image/video processing and machine learning. FPGA vendors provide high …
such as image/video processing and machine learning. FPGA vendors provide high …
Advanced compressor tree synthesis for FPGAs
M Kumm, J Kappauf - IEEE Transactions on Computers, 2018 - ieeexplore.ieee.org
This work presents novel methods for the optimization of compressor trees for FPGAs as
required in many arithmetic computations. As demonstrated in recent work, important key …
required in many arithmetic computations. As demonstrated in recent work, important key …
Optimal constant multiplication using integer linear programming
M Kumm - IEEE Transactions on Circuits and Systems II …, 2018 - ieeexplore.ieee.org
Constant multiplication circuits can be realized multiplierless by using additions,
subtractions, and bit-shifts. The problem of finding a multiplication circuit with minimum …
subtractions, and bit-shifts. The problem of finding a multiplication circuit with minimum …
Pipelined compressor tree optimization using integer linear programming
M Kumm, P Zipf - 2014 24th International Conference on Field …, 2014 - ieeexplore.ieee.org
Compressor trees offer an effective realization of the multiple input addition needed by many
arithmetic operations. However, map** the commonly used carry save adders (CSA) of …
arithmetic operations. However, map** the commonly used carry save adders (CSA) of …
Table-based versus shift-and-add constant multipliers for FPGAs
The multiplication by a constant is a frequently used operation. To implement it on Field
Programmable Gate Arrays (FPGAs), the state of the art offers two completely different …
Programmable Gate Arrays (FPGAs), the state of the art offers two completely different …
[LIVRE][B] Multiple constant multiplication optimizations for field programmable gate arrays
M Kumm, P Zipf - 2016 - Springer
As silicon technology advances, field programmable gate arrays appear to gain ground
against the traditional ASIC project starts, reaching out to form the mainstream …
against the traditional ASIC project starts, reaching out to form the mainstream …
Optimal single constant multiplication using ternary adders
The single constant coefficient multiplication is a frequently used operation in many numeric
algorithms. Extensive previous work is available on how to reduce constant multiplications to …
algorithms. Extensive previous work is available on how to reduce constant multiplications to …
A high-speed floating-point multiply-accumulator based on fpgas
B Zhou, G Wang, G Jie, Q Liu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed.
It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC) …
It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC) …
Multiple constant multiplication algorithm for high-speed and low-power design
In this brief, Radix-2 r arithmetic is applied to the multiple constant multiplication (MCM)
problem. Given a number M of nonnegative constants with a bit length N, we determine the …
problem. Given a number M of nonnegative constants with a bit length N, we determine the …