Fundamental thermal limits on data retention in low-voltage CMOS latches and SRAM

E Rezaei, M Donato, WR Patterson… - … on Device and …, 2020 - ieeexplore.ieee.org
Ultra-low-power systems with substantial computing capacity require latches and SRAMs to
operate at extremely low supply voltages. However, with aggressive technology scaling …

High Quality of 0.18 μm CMOS 5.2 GHz cascode LNA for RFID tag applications

HC Yang, SH Peng, SJ Wang, MC Wang… - … Symposium on Next …, 2013 - ieeexplore.ieee.org
An operation in 1.8 V supply voltage single-ended cascode low-noise amplifier (LNA)
structure was launched. This designed circuit provided the lower noise figure and matched …

A sub-threshold noise transient simulator based on integrated random telegraph and thermal noise modeling

M Donato, RI Bahar, WR Patterson… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Near-threshold and sub-threshold voltage designs have been identified as possible
solutions to overcome the limitations introduced by energy consumption in modern very …

A simulation framework for analyzing transient effects due to thermal noise in sub-threshold circuits

M Donato, RI Bahar, W Patterson… - Proceedings of the 25th …, 2015 - dl.acm.org
Noise analysis in nonlinear logic circuits requires models that take into account time-varying
biasing conditions. When considering thermal noise, which moves the circuit away from its …

Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework

P Jannaty, FC Sabou, ST Le, M Donato… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
As CMOS technology continues the path of miniaturization, noise-induced fluctuations raise
heightened reliability concerns. In previous work, an analytical framework based on Markov …

A fast simulator for the analysis of sub-threshold thermal noise transients

M Donato, RI Bahar, W Patterson… - Proceedings of the 53rd …, 2016 - dl.acm.org
The gate length of CMOS transistors is continuing to shrink down to the sub-10nm region
and operating voltages are moving toward near-threshold and even sub-threshold values …

Thermal noise-induced error simulation framework for subthreshold CMOS SRAM

E Rezaei, M Donato, W Patterson… - 2019 IEEE SOI-3D …, 2019 - ieeexplore.ieee.org
Accurate error-rate modeling in ultra-low-power subthreshold CMOS circuitry is needed to
predict reliability. In this study, we extend our stochastic time-domain error simulation …

[PDF][PDF] High Quality of 0.18μm CMOS 5.2 GHz Cascode LNA for RFID Tag Applications

CHL Chin - researchgate.net
An operation in 1.8 V supply voltage single-ended cascode lownoise amplifier (LNA)
structure was launched. This designed circuit provided the lower noise figure and matched …

[ZITATION][C] Noise Modeling and Simulation Frameworks for the Design of Sub-threshold Ultimate CMOS Circuits

M Donato - 2016 - Brown University PROVIDENCE …