To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Power density continues to increase exponentially with each new technology generation,
posing a major challenge for thermal management in modern processors. Much past work …

The advent of deep sub-micron technology has recently highlighted the criticality of the on-
chip interconnects. As diminishing feature sizes have led to increases in global wiring …

Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D)
chip structures are envisioned as a viable solution to skyrocketing transistor densities and …

The increased deployment of System-on-Chip designs has drawn attention to the limitations
of on-chip interconnects. As a potential solution to these limitations, Networks-on-Chip …

ABSTRACT Niklaus Emil Wirth introduced the innovative concept of Programming=
Algorithm+ Data Structure [109]. Inspired by this, we advance the concept to the next level by …

Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip
(SoC) designs supporting numerous homogeneous and heterogeneous functional blocks …

Power densities have been increasing rapidly at all levels of server systems. To counter the
high temperatures resulting from these densities, systems researchers have recently started …

Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D
IC technology, is motivated to achieve lower latency, lower power consumption, and higher …

Network-on-chip (NoC) has become a critical shared resource in the emerging Chip
Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across …