Large scale data centers (DC) and high performance computing (HPC) systems require
more and more computing power at higher energy efficiency. They are already consuming …

We examine the current performance and future demands of interconnects to and on silicon
chips. We compare electrical and optical interconnects and project the requirements for …

A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is
presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 …

Computing modules in typical data center nodes or server racks consist of several multicore
chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter …

Synchronous CDMA/spread spectrum methods, devices, and systems are used to suppress
crosstalk in clock-forwarded on-chip interconnects. Transmitting a spread spectrum signal …

Interconnect architectures which leverage high-bandwidth optical channels offer a promising
solution to address the increasing chip-to-chip I/O bandwidth demands. This paper …

Improving the energy efficiency of computer communication is becoming more and more
important as the world is creating a massive amount of data, while the interface has been a …

A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate
topology with purely digital blocks to substantially reduce power consumption. The receiver …

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with
rapid transition times to support power efficient signaling over a wide range of effective …

Improvements in signaling methods, circuits and process technology have allowed
input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this …