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Temperature effect on hetero structure junctionless tunnel FET
SB Rahi, B Ghosh, B Bishnoi - Journal of semiconductors, 2015 - iopscience.iop.org
For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure
junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an …
junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an …
Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor
Y Goswami, B Ghosh, PK Asthana - RSC Advances, 2014 - pubs.rsc.org
In this paper, the analog performance of a Si double gate Junctionless Tunnel Field Effect
Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V …
Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V …
A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET
SB Rahi, B Ghosh, P Asthana - Journal of semiconductors, 2014 - iopscience.iop.org
We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using
AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and …
AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and …
High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply
PK Asthana - Journal of semiconductors, 2015 - iopscience.iop.org
Abstract We present a GaSb/InAs junctionless tunnel FET and investigate its static device
characteristics. The proposed structure presents tremendous performance at a very low …
characteristics. The proposed structure presents tremendous performance at a very low …
Design of tunneling field-effect transistor (TFET) with AlxGa1−xAS/InxGa1−xAs hetero-junction
In this paper a hetero-junction tunnel field effect transistor (HJ-TFET) with the channel length
of 20 nm has been introduced and simulated in which the source/channel hetero-junction is …
of 20 nm has been introduced and simulated in which the source/channel hetero-junction is …
Junctionless tunnel field effect transistor with enhanced performance using III–V semiconductor
Y Goswami, BMM Tripathi, P Asthana… - Journal of Low Power …, 2013 - ingentaconnect.com
In this paper, the performance of a double gate Junctionless Tunnel Field Effect Transistor
has been enhanced with very decent characteristics using a ternary III–V semiconductor …
has been enhanced with very decent characteristics using a ternary III–V semiconductor …
[PDF][PDF] A Comparative Analysis of Tunneling FET characteristics for low power digital circuits
KS Thorat, SM Turkane - ResearchGate, 2014 - Citeseer
The technology used in today's transistors is called “field effect” whereby voltage induces an
electron channel that activates the transistor. But field effect technology is approaching its …
electron channel that activates the transistor. But field effect technology is approaching its …
Si/Ge 异质结双栅隧穿场效应晶体管 TCAD 仿真研究
王菡滨， 刘梦新， 毕津顺， **伟 - Microelectronics, 2021 - opticsjournal.net
摘要Si/Ge 异质结双栅隧穿场效应晶体管(DGTFET) 较传统硅基DGTFET 有更好的电学性能.
文章基于Sentaurus TCAD 仿真软件, 构建了有/无Pocket 两种结构的Si/Ge 异质结DGTFET …
文章基于Sentaurus TCAD 仿真软件, 构建了有/无Pocket 两种结构的Si/Ge 异质结DGTFET …
Device Physics of Germanium-Junctionless Tunnel Field Effect Transistor and an Approach to Optimize I on/I off by Drain Engineering and Work Function Engineering
B Ghosh, P Bal, P Mondal… - Journal of Low Power …, 2014 - ingentaconnect.com
We demonstrate the physics behind the operation of Germanium (Ge) junctionless tunnel
field effect transistor (JLTFET) for high performance and low power (LP) logic applications …
field effect transistor (JLTFET) for high performance and low power (LP) logic applications …