High-performance special function unit for programmable 3-D graphics processors
An high-speed special function unit (SFU) is presented in this paper. The system supports
the single-precision IEEE-754 floating-point standard and implements faithfully rounded …
the single-precision IEEE-754 floating-point standard and implements faithfully rounded …
An embedded stream processor core based on logarithmic arithmetic for a low-power 3-D graphics SoC
BG Nam, HJ Yoo - IEEE Journal of Solid-State Circuits, 2009 - ieeexplore.ieee.org
A low-power and high-performance 4-way 32-bit stream processor core is developed for
handheld low-power 3-D graphics systems. It contains a floating-point unified matrix, vector …
handheld low-power 3-D graphics systems. It contains a floating-point unified matrix, vector …
A floating-point unit for 4D vector inner product with reduced latency
D Kim, LS Kim - IEEE Transactions on computers, 2008 - ieeexplore.ieee.org
This paper presents the algorithm and implementation of a new high-performance functional
unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is …
unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is …
An energy-efficient mobile vertex processor with multithread expanded VLIW architecture and vertex caches
In this paper, a 3-D vertex processor with a floating-point four-threaded and four-issue
expanded VLIW architecture and vertex caches for mobile multimedia applications is …
expanded VLIW architecture and vertex caches for mobile multimedia applications is …
Homogeneous stream processors with embedded special function units for high-utilization programmable shaders
We embed special function units (SFUs) in homogeneous stream processors (SPs) within a
graphics processing unit (GPU), to improve its performance in running modern …
graphics processing unit (GPU), to improve its performance in running modern …
Flexible-assignment calibration technique for mismatch-constrained digital-to-analog converters
This paper presents a calibration technique for mismatch-constrained digital-to-analog
converters (DACs). The architecture is based on a fully flexible unit current cell assignment …
converters (DACs). The architecture is based on a fully flexible unit current cell assignment …
[PDF][PDF] A new frame memory compression algorithm with DPCM and VLC in a 4× 4 block
Frame memory compression (FMC) is a technique to reduce memory bandwidth by
compressing the video data to be stored in the frame memory. This paper proposes a new …
compressing the video data to be stored in the frame memory. This paper proposes a new …
An Advanced Method of Testing Memories Using a Vedic March Algorithm
K Rayudu, Jahagirdar, PS Rao - IETE Journal of Research, 2024 - Taylor & Francis
Nowadays, as the technology grows the size of the chip decreases, and RAM testing
becomes more critical whose input and output ports are not controlled directly through the …
becomes more critical whose input and output ports are not controlled directly through the …
Methods of and apparatus for processing computer graphics
J Nystad, E Faye-Lund - US Patent 8,115,783, 2012 - Google Patents
US8115783B2 - Methods of and apparatus for processing computer graphics - Google Patents
US8115783B2 - Methods of and apparatus for processing computer graphics - Google Patents …
US8115783B2 - Methods of and apparatus for processing computer graphics - Google Patents …
A low cost tile-based 3D graphics full pipeline with real-time performance monitoring support for OpenGL ES in consumer electronics
RT Gu, TC Yeh, WS Hunag, TY Huang… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
This paper presents a 3D graphics engine which is specifically designed to minimize the
hardware cost while providing sufficient computing capability for consumer electronics with …
hardware cost while providing sufficient computing capability for consumer electronics with …