Signal integrity design for high-speed digital circuits: Progress and directions
This paper reviews recent progress and future directions of signal integrity design for high-
speed digital circuits, focusing on four areas: signal propagation on transmission lines …
speed digital circuits, focusing on four areas: signal propagation on transmission lines …
Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial
The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …
precision of their clocking infrastructure. For future applications, such as microprocessor …
Modeling and analysis of high-speed I/O links
Improvements in signaling methods, circuits and process technology have allowed
input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this …
input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this …
Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology
Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive
equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A …
equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A …
[LIBRO][B] High speed digital design: design of high speed interconnects and signaling
H Zhang, S Krooswyk, J Ou - 2015 - books.google.com
High Speed Digital Design discusses the major factors to consider in designing a high
speed digital system and how design concepts affect the functionality of the system as a …
speed digital system and how design concepts affect the functionality of the system as a …
The future of electrical I/O for microprocessors
High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in
terms of power and performance largely due to advances in equalization and clocking …
terms of power and performance largely due to advances in equalization and clocking …
Fast and accurate estimation of statistical eye diagram for nonlinear high-speed links
X Chu, W Guo, J Wang, F Wu, Y Luo… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
A fast and accurate statistical eye diagram estimation method for high-speed nonlinear links
is proposed in this article. Probability density functions (PDFs) of output responses are …
is proposed in this article. Probability density functions (PDFs) of output responses are …
Fast estimation of a statistical eye diagram for nonlinear high-speed links based on the minimum required order of the multiple edge response method
J Wang, Y Luo, W Guo, F Wu… - IEEE Transactions on Very …, 2022 - ieeexplore.ieee.org
With the increase in nonlinear effects of high-speed links, the higher order multiple edge
response (MER) method is widely used to accurately evaluate high-speed link performance …
response (MER) method is widely used to accurately evaluate high-speed link performance …
Estimation method for statistical eye diagram in a nonlinear digital channel
CC Chou, SY Hsu, TL Wu - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
An estimation method for statistical eye diagram in a digital channel with nonlinear circuitry
is proposed, which is based on the superposition of multiple bit pattern responses method …
is proposed, which is based on the superposition of multiple bit pattern responses method …
Efficient and accurate eye diagram prediction for high speed signaling
This paper introduces an accumulative prediction method to predict the eye diagram for high
speed signaling systems. We use the step responses of pull-up and pull-down to extract the …
speed signaling systems. We use the step responses of pull-up and pull-down to extract the …