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SARLock: SAT attack resistant logic locking
Logic locking is an Intellectual Property (IP) protection technique that thwarts IP piracy,
hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken …
hardware Trojans, reverse engineering, and IC overproduction. Researchers have taken …
Fault simulation and emulation tools to augment radiation-hardness assurance testing
As of 2013, the gold standard for assessing radiation-hardness assurance (RHA) for a
system, subsystem, or a component is accelerated radiation testing and/or pulsed laser …
system, subsystem, or a component is accelerated radiation testing and/or pulsed laser …
Characterizing the impact of intermittent hardware faults on programs
L Rashid, K Pattabiraman… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Extreme complimentary metal-oxide-semiconductor (CMOS) technology scaling is causing
significant concerns in the reliability of computer systems. Intermittent hardware errors are …
significant concerns in the reliability of computer systems. Intermittent hardware errors are …
Instruction-level impact analysis of low-level faults in a modern microprocessor controller
We investigate the correlation between low-level faults in the control logic of a modern
microprocessor and their instruction-level impact on the execution of typical workload. Such …
microprocessor and their instruction-level impact on the execution of typical workload. Such …
An effective method to identify microarchitectural vulnerabilities in gpus
Graphics Processing Units (GPUs) are increasingly adopted in several domains where
reliability is fundamental, such as self-driving cars and autonomous systems. Unfortunately …
reliability is fundamental, such as self-driving cars and autonomous systems. Unfortunately …
FIMSIM: A fault injection infrastructure for microarchitectural simulators
Fault injection is a widely used approach for experiment-based dependability evaluation.
Injecting faults to microarchitectural simulators is particularly appealing for researchers …
Injecting faults to microarchitectural simulators is particularly appealing for researchers …
[PDF][PDF] Efficient fault-injection-based assessment of software-implemented hardware fault tolerance
HB Schirmeier - 2016 - eldorado.tu-dortmund.de
With continuously shrinking semiconductor structure sizes and lower supply voltages, the
per-device susceptibility to transient and permanent hardware faults is on the rise. A class of …
per-device susceptibility to transient and permanent hardware faults is on the rise. A class of …
Board-level fault diagnosis using Bayesian inference
Z Zhang, Z Wang, X Gu… - 2010 28th VLSI Test …, 2010 - ieeexplore.ieee.org
Increasing integration densities and high operating speeds are leading to subtle
manifestations of defects at the board level. Board-level functional test is therefore …
manifestations of defects at the board level. Board-level functional test is therefore …
Workload-driven selective hardening of control state elements in modern microprocessors
We present a method for selective hardening of control state elements against soft errors in
modern microprocessors. In order to effectively allocate resources, our method seeks to rank …
modern microprocessors. In order to effectively allocate resources, our method seeks to rank …
Comparing the effects of intermittent and transient hardware faults on programs
The trends of shrinking device geometries, lower voltages and higher frequencies in modern
processors are expected to increase the rate of intermittent faults. This requires the design of …
processors are expected to increase the rate of intermittent faults. This requires the design of …