As basic components, optimizing power consumption of flip-flops (FFs) can significantly
reduce the power of digital systems. In this article, an energy-efficient retentive true-single …

We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically
reconfigurable interconnects and memory. Versa leverages reconfigurable functional units …

We present a systematic evaluation and optimization of a complex bio-medical signal
processing application on the BrainWave prototype system, targeted towards ambulatory …

Flip-flop research in recent years has been motivated by power-and/or energy-efficient
designs. Flip-flop power is based on data activity (DA), which in many applications ranges …

State-of-the-art digital low-dropout regulators (LDOs) have shown competitive dynamic load
regulation at a scaled output capacitor size. However, achieving high power-supply …

For a network-on-chip (NoC) with multiple voltage/frequency domains, metastability hurts the
reliability during the clock-domain crossing, especially in the near-threshold-voltage (NTV) …

This article presents a timing slack inference and clock frequency adaption technique,
named TICA, to mitigate the large and pessimistic timing guardband reserved for process …

This work presents a 1-8b reconfigurable digital SRAM compute-in-memory (CIM) macro,
which significantly improves array utilization and energy efficiency under different input and …

This article presents an ultra-low-power D flip-flop (FF) named clock-load reduced FF
(CRFF), which employs 23 transistors with only three clock load transistors to support fully …

Conventional high-performance flip-flops suffer from large power consumption at the
nominal supply region and unreliable operation in the low-voltage region. To overcome …