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Systolic array component combining multiple integer and floating-point data types
T Elmer, TA Volpe - US Patent 11,816,446, 2023 - Google Patents
G06F7/48—Methods or arrangements for performing computations using exclusively
denominational number representation, eg using binary, ternary, decimal representation …
denominational number representation, eg using binary, ternary, decimal representation …
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
T Elmer - US Patent 11,467,806, 2022 - Google Patents
Systems and methods are provided to perform multiply accumulate operations of normalized
numbers in a systolic array to enable greater computational density, reduce the size of …
numbers in a systolic array to enable greater computational density, reduce the size of …
Multiple busses interleaved in a systolic array
TA Volpe, VK Palisetti, T Elmer, KK Seshadri… - US Patent …, 2022 - Google Patents
Systems and methods are provided to enable parallelized multiply-accumulate operations in
a systolic array. Each row of the systolic array can include multiple busses enabling …
a systolic array. Each row of the systolic array can include multiple busses enabling …
Multiple busses within a systolic array processing element
TA Volpe, T Elmer, KK Seshadri - US Patent 11,422,773, 2022 - Google Patents
US11422773B1 - Multiple busses within a systolic array processing element - Google Patents
US11422773B1 - Multiple busses within a systolic array processing element - Google Patents …
US11422773B1 - Multiple busses within a systolic array processing element - Google Patents …
Systolic array with efficient input reduction and extended array performance
PG Meyer, TA Volpe, R Diamant, JW Bowman… - US Patent …, 2024 - Google Patents
2022-06-28 Assigned to AMAZON TECHNOLOGIES, INC. reassignment AMAZON
TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
Multiple accumulate busses in a systolic array
TA Volpe, S Amirineni, T Elmer - US Patent 11,762,803, 2023 - Google Patents
G06F7/48—Methods or arrangements for performing computations using exclusively
denominational number representation, eg using binary, ternary, decimal representation …
denominational number representation, eg using binary, ternary, decimal representation …
FPGA specialist processing block for machine learning
M Langhammer, D Chen, JR Bergendahl - US Patent 11,494,186, 2022 - Google Patents
The present disclosure describes a digital signal processing (DSP) block that includes a
plurality of columns of weight registers and a plurality of inputs configured to receive a first …
plurality of columns of weight registers and a plurality of inputs configured to receive a first …
Systolic multiply delayed accumulate processor architecture
T Elmer - US Patent 11,842,169, 2023 - Google Patents
G06F7/48—Methods or arrangements for performing computations using exclusively
denominational number representation, eg using binary, ternary, decimal representation …
denominational number representation, eg using binary, ternary, decimal representation …
FPGA specialist processing block for machine learning
M Langhammer, D Chen, JR Bergendahl - US Patent 11,520,584, 2022 - Google Patents
The present disclosure describes a digital signal processing (DSP) block that includes a
plurality of columns of weight registers and a plurality of inputs configured to receive a first a …
plurality of columns of weight registers and a plurality of inputs configured to receive a first a …
Application specific integrated circuit accelerators
MA Gunter, IV Leichner, C Henry… - US Patent …, 2025 - freepatentsonline.com
An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and
multiple controllable bus lines configured to convey data among the systolic array of cells, in …
multiple controllable bus lines configured to convey data among the systolic array of cells, in …