Towards automated RISC-V microarchitecture design with reinforcement learning

C Bai, J Zhai, Y Ma, B Yu, MDF Wong - Proceedings of the AAAI …, 2024 - ojs.aaai.org
Microarchitecture determines the implementation of a microprocessor. Designing a
microarchitecture to achieve better performance, power, and area (PPA) trade-off has been …

An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies

T Gao, Y Wang, M Zhu, X Wu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
The optimization of RISC-V designs, encompassing both microarchitecture and CAD tool
parameters, is a great challenge due to an extensive and high-dimensional search space …

APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration

X Zhao, T Gao, Z Wu, Z Bi, C Yan… - … on Computer-Aided …, 2024 - ieeexplore.ieee.org
The synthesizable and parameterizable RISC-V microarchitecture, combined with multi-
objective optimization-based Design Space Exploration (DSE), facilitates agile adaptation to …