Cooling future system-on-chips with diamond inter-tiers

M Malakoutian, A Kasperovich, D Rich, K Woo… - Cell Reports Physical …, 2023 - cell.com
Heat spreading is critical in reducing the overall junction temperature of monolithic system-
on-chips (SoCs) and high-heat-flux radio frequency (RF) applications. Bulk diamond has the …

Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration

J Knechtel, O Sinanoglu, IAM Elfadel… - IPSJ Transactions on …, 2017 - jstage.jst.go.jp
Three-dimensional (3D) integration of electronic chips has been advocated by both industry
and academia for many years. It is acknowledged as one of the most promising approaches …

IR-drop analysis of hybrid bonded 3D-ICs with backside power delivery and μ-& n-TSVs

G Sisto, B Chehab, B Genneret, R Baert… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
We present an IR-drop analysis of hybrid bonded 3D-ICs Power Delivery Network with
backside metals and buried power rail. Two different options for the backside to frontside …

Architecting large-scale SRAM arrays with monolithic 3D integration

J Kong, YH Gong, SW Chung - 2017 IEEE/ACM International …, 2017 - ieeexplore.ieee.org
In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration
technology. We introduce M3D-based SRAM arrays with three different ways of integration …

Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits

D Rich, A Kasperovich, M Malakoutian… - 2023 60th ACM/IEEE …, 2023 - ieeexplore.ieee.org
We address the thermal challenge of ultra-dense 3D (eg, monolithic 3D) integrated circuits
with multiple high-speed computing engines in the 3D stack. We present a new thermal …

Reliable power delivery and analysis of power-supply noise during testing in monolithic 3D ICs

A Koneru, A Todri-Sanial… - 2019 IEEE 37th VLSI …, 2019 - ieeexplore.ieee.org
Monolithic 3D (M3D) integration offers significant performance, power, and area benefits.
However, the design of a reliable M3D power-delivery network (PDN) is challenging due to …

Enhanced power delivery pathfinding for emerging 3-d integration technology

AB Kahng, S Kang, S Kim, B Xu - IEEE Transactions on Very …, 2020 - ieeexplore.ieee.org
In advanced technology nodes, emerging 3-D integration technology is a promising “More
Than Moore” lever for continued scaling of system capability and value. In the 3-D integrated …

Power delivery pathfinding for emerging die-to-wafer integration technology

AB Kahng, S Kang, S Kim, K Samadi… - … Design, Automation & …, 2019 - ieeexplore.ieee.org
In advanced technology nodes, emerging die-to-wafer (D2W) integration technology is a
promising" More Than Moore" lever for continued scaling of system capability and value. In …

Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules

L Mattii, D Milojevic, P Debacker… - Journal of Micro …, 2018 - spiedigitallibrary.org
Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply
interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells …

Power-supply noise analysis for monolithic 3D ICs using electrical and thermal co-simulation

A Koneru, A Todri-Sanial… - 2018 25th IEEE …, 2018 - ieeexplore.ieee.org
Reliable power-delivery network (PDN) design is a major challenge for monolithic 3D (M3D)
ICs due to higher power density and current demand per unit area, higher parasitics of …