Secure hash algorithms and the corresponding FPGA optimization techniques
Cryptographic hash functions are widely used primitives with a purpose to ensure the
integrity of data. Hash functions are also utilized in conjunction with digital signatures to …
integrity of data. Hash functions are also utilized in conjunction with digital signatures to …
FPGA implementations of the round two SHA-3 candidates
B Baldwin, A Byrne, L Lu, M Hamilton… - … Conference on Field …, 2010 - ieeexplore.ieee.org
The second round of the NIST-run public competition is underway to find a new hash
algorithm (s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents …
algorithm (s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents …
Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates
M Knezevic, K Kobayashi, J Ikegami… - … Transactions on Very …, 2011 - ieeexplore.ieee.org
The first contribution of our paper is that we propose a platform, a design strategy, and
evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 …
evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 …
On efficiency enhancement of SHA-3 for FPGA-based multimodal biometric authentication
Synchronized padder block and a compact-dynamic round constant (RC) generator to
achieve highly efficient Keccak architecture are proposed in this work. The proposed design …
achieve highly efficient Keccak architecture are proposed in this work. The proposed design …
Intelligent parking reservation service on the Internet
K Inaba, M Shibui, T Naganawa… - … 2001 Symposium on …, 2001 - ieeexplore.ieee.org
The described intelligent parking service is a part of an ITS (intelligent transportation system)
in which parking facilities are conceived of in terms of various new functions which they can …
in which parking facilities are conceived of in terms of various new functions which they can …
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA
JL Beuchat, E Okamoto… - … Conference on Field …, 2010 - ieeexplore.ieee.org
We propose compact architectures of the SHA-3 candidates BLAKE-32 and BLAKE-64 for
several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the …
several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the …
Gmu hardware api for authenticated ciphers
In this paper, we propose a universal hardware API for authenticated ciphers, which can be
used in any future implementations of authenticated ciphers submitted to the CAESAR …
used in any future implementations of authenticated ciphers submitted to the CAESAR …
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl
This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption
standard (AES)(encryption, decryption, and key expansion) and the cryptographic hash …
standard (AES)(encryption, decryption, and key expansion) and the cryptographic hash …
A universal hardware API for authenticated ciphers
In this paper, we propose a universal hardware Application Programming Interface (API) for
authenticated ciphers. In particular, our API is intended to meet the requirements of all …
authenticated ciphers. In particular, our API is intended to meet the requirements of all …
Prototy** platform for performance evaluation of SHA-3 candidates
K Kobayashi, J Ikegami, M Knežević… - … Security and Trust …, 2010 - ieeexplore.ieee.org
The objective of the SHA-3 NIST competition is to select, from multiple competing
candidates, a standard algorithm for cryptographic hashing. The selected winner must have …
candidates, a standard algorithm for cryptographic hashing. The selected winner must have …