A survey on data storage and placement methodologies for cloud-big data ecosystem

S Mazumdar, D Seybold, K Kritikos, Y Verginadis - Journal of Big Data, 2019 - Springer
Currently, the data to be explored and exploited by computing systems increases at an
exponential rate. The massive amount of data or so-called “Big Data” put pressure on …

Survey of scheduling techniques for addressing shared resources in multicore processors

S Zhuravlev, JC Saez, S Blagodurov… - ACM Computing …, 2012 - dl.acm.org
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for
modern computing platforms and will most likely continue to be dominant well into the …

Simba: Scaling deep-learning inference with multi-chip-module-based architecture

YS Shao, J Clemons, R Venkatesan, B Zimmer… - Proceedings of the …, 2019 - dl.acm.org
Package-level integration using multi-chip-modules (MCMs) is a promising approach for
building large-scale systems. Compared to a large monolithic die, an MCM combines many …

Clearing the clouds: a study of emerging scale-out workloads on modern hardware

M Ferdman, A Adileh, O Kocberber, S Volos… - Acm sigplan …, 2012 - dl.acm.org
Emerging scale-out workloads require extensive amounts of computational resources.
However, data centers using modern server hardware face physical constraints in space …

Tangram: Optimized coarse-grained dataflow for scalable nn accelerators

M Gao, X Yang, J Pu, M Horowitz… - Proceedings of the Twenty …, 2019 - dl.acm.org
The use of increasingly larger and more complex neural networks (NNs) makes it critical to
scale the capabilities and efficiency of NN accelerators. Tiled architectures provide an …

A data placement strategy in scientific cloud workflows

D Yuan, Y Yang, X Liu, J Chen - Future Generation Computer Systems, 2010 - Elsevier
In scientific cloud workflows, large amounts of application data need to be stored in
distributed data centres. To effectively store these data, a data manager must intelligently …

Die-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache

D Jevdjic, S Volos, B Falsafi - ACM SIGARCH Computer Architecture …, 2013 - dl.acm.org
Recent research advocates using large die-stacked DRAM caches to break the memory
bandwidth wall. Existing DRAM cache designs fall into one of two categories---block-based …

Softsku: Optimizing server architectures for microservice diversity@ scale

A Sriraman, A Dhanotia, TF Wenisch - Proceedings of the 46th …, 2019 - dl.acm.org
The variety and complexity of microservices in warehouse-scale data centers has grown
precipitously over the last few years to support a growing user base and an evolving product …

Bingo spatial data prefetcher

M Bakhshalipour, M Shakerinava… - … Symposium on High …, 2019 - ieeexplore.ieee.org
Applications extensively use data objects with a regular and fixed layout, which leads to the
recurrence of access patterns over memory regions. Spatial data prefetching techniques …

Ubik: Efficient cache sharing with strict QoS for latency-critical workloads

H Kasture, D Sanchez - ACM Sigplan Notices, 2014 - dl.acm.org
Chip-multiprocessors (CMPs) must often execute workload mixes with different performance
requirements. On one hand, user-facing, latency-critical applications (eg, web search) need …