Evaluating STT-RAM as an energy-efficient main memory alternative
In this paper, we explore the possibility of using STT-RAM technology to completely replace
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
A survey of architectural techniques for managing process variation
S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …
slow down and even pause technological scaling, and mitigation of it is the way to continue …
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that
is a potential universal memory that could replace SRAM in processor caches. This paper …
is a potential universal memory that could replace SRAM in processor caches. This paper …
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
High density, low leakage and non-volatility are the attractive features of Spin-Transfer-
Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a …
Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a …
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
Large last-level caches (L 3 Cs) are frequently used to bridge the performance and power
gap between processor and memory. Although traditional processors implement caches as …
gap between processor and memory. Although traditional processors implement caches as …
DRAM refresh mechanisms, penalties, and trade-offs
Ever-growing application data footprints demand faster main memory with larger capacity.
DRAM has been the technology choice for main memory due to its low latency and high …
DRAM has been the technology choice for main memory due to its low latency and high …
Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era
Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …
significant threat to the continued scaling of transistor dimensions. Such parameter …
Characterizing and mitigating the impact of process variations on phase change based memory systems
W Zhang, T Li - Proceedings of the 42nd Annual IEEE/ACM …, 2009 - dl.acm.org
Dynamic Random Access Memory (DRAM) has been used in main memory design for
decades. However, DRAM consumes an increasing power budget and faces difficulties in …
decades. However, DRAM consumes an increasing power budget and faces difficulties in …
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for Universal
memory. However, there are two challenges to using STT-RAM in memory system design:(1) …
memory. However, there are two challenges to using STT-RAM in memory system design:(1) …
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
N **g, Y Shen, Y Lu, S Ganapathy, Z Mao… - ACM SIGARCH …, 2013 - dl.acm.org
The heavily-threaded data processing demands of streaming multiprocessors (SM) in a
GPGPU require a large register file (RF). The fast increasing size of the RF makes the area …
GPGPU require a large register file (RF). The fast increasing size of the RF makes the area …