Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms

CH Chiu, DL Lin, TW Huang - 2023 IEEE/ACM International …, 2023 - ieeexplore.ieee.org
Many EDA applications are extremely sparse, irregular, and control-flow intensive.
Parallelizing this type of application can benefit from the ability to express dynamic task …

GSAP: A GPU-Accelerated Stochastic Graph Partitioner

CC Chang, B Zhang, TW Huang - Proceedings of the 53rd International …, 2024 - dl.acm.org
Graph partitioning is essential for understanding the structure of a dataset, such as social
networks and web pages. Among various graph partitioners, stochastic block partitioning …

FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array

S Jiang, R Fu, L Burgholzer, R Wille, TY Ho… - Proceedings of the 53rd …, 2024 - dl.acm.org
Quantum circuit simulator (QCS) is essential for designing quantum algorithms because it
assists researchers in understanding how quantum operations work without access to …

An Experimental Study of Dynamic Task Graph Parallelism for Large-Scale Circuit Analysis Workloads

CH Chiu, TW Huang - 2024 IEEE Computer Society Annual …, 2024 - ieeexplore.ieee.org
Many circuit analysis workloads incorporate complex execution logic under dynamic control
flow, such as branch-and-bound techniques, on-the-fly pruning and recursive decomposition …

Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System

TW Huang, B Zhang, DL Lin, CH Chiu - Proceedings of the 2024 …, 2024 - dl.acm.org
Static timing analysis (STA) is an integral part in the overall design flow because it verifies
the expected timing behaviors of a circuit. However, as the circuit complexity continues to …

[PDF][PDF] Reinforcement Learning-generated Topological Order for Dynamic Task Graph Scheduling

CH Chiu, C Morchdi, Y Zhou… - IEEE High …, 2024 - tsung-wei-huang.github.io
Dynamic task graph scheduling (DTGS) has become a powerful tool for parallel and
heterogeneous applications, such as static timing analysis and large-scale machine …

An Efficient Task-Parallel Pipeline Programming Framework

CH Chiu, Z **ong, Z Guo, TW Huang, Y Lin - Proceedings of the …, 2024 - dl.acm.org
The pipeline is a fundamental pattern to parallelize a series of stage tasks over a sequence
of data in loops. Mainstream pipeline programming frameworks count on data abstractions …

[PDF][PDF] HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner

WL Lee, DL Lin, CH Chiu… - IEEE/ACM Asia …, 2025 - tsung-wei-huang.github.io
Hypergraph partitioning plays a critical role in computer-aided design (CAD) because it
allows us to break down a large circuit into several manageable pieces that facilitate efficient …

A Resource-efficient Task Scheduling System using Reinforcement Learning

C Morchdi, CH Chiu, Y Zhou… - 2024 29th Asia and …, 2024 - ieeexplore.ieee.org
Computer-aided design (CAD) tools typically incorporate thousands or millions of functional
tasks and dependencies to implement various synthesis and analysis algorithms. Efficiently …

[PDF][PDF] PathGen: An Efficient Parallel Critical Path Generation Algorithm

C Chang, B Zhang, CH Chiu, DL Lin… - IEEE/ACM Asia …, 2025 - tsung-wei-huang.github.io
Abstract Critical Path Generation (CPG) is fundamental for many static timing analysis (STA)
applications. As the circuit complexity continues to increase, CPG runtime has quickly …