Clusters of PCs have become very popular to build high performance computers. These
machines use commodity PCs linked by a high speed interconnect. Routing is one of the …

We compare the performance of four admission control algorithms-one parameter-based
and three measurement-based-for controlled-load service. The parameter-based admission …

Most standard cluster interconnect technologies are flexible with respect to network
topology. This has spawned a substantial amount of research on topology-agnostic routing …

The design of scalable and reliable interconnection networks for multicore chips (NoCs)
introduces new design constraints like power consumption, area, and ultra low latencies …

The majority of current network on chip (NoC) architectures employ mesh topology and use
simple static routing, to reduce power and area. However, regular mesh topology is …

The design of scalable and reliable interconnection networks for system on chips (SoCs)
introduce new design constraints not present in current multicomputer systems. Although …

The design of NoCs for multi-core chips introduces new design constraints like power
consumption, area, and ultra low latencies. Although 2D meshes are preferred …

Providing highly flexible connectivity is a major architectural challenge for hardware
implementation of reconfigurable neural networks. We perform an analytical evaluation and …

The high-performance computing domain is enriching with the inclusion of networks-on-chip
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …

Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing
domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they …