In this paper, we address an open problem of zero-shot learning. Its principle is based on
learning a map** that associates feature vectors extracted from ie images and attribute …

Despite decades of innovation, existing hash tables fail to achieve peak performance on
modern hardware. Built around a relatively simple computation, ie, a hash function, which in …

Relentless technology scaling has made transistors more vulnerable to soft, or transient,
errors. To keep systems robust against these, current error detection techniques use …

Processors with 100s of threads of execution are among the state-of-the-art in high-end
computing systems. This transition to many-core computing has required the community to …

With the spreading of multi-core architectures, operating systems and applications are
becoming increasingly more concurrent and their scalability is often limited by the primitives …

Enabling efficient fine-grained task parallelism is a significant challenge for hardware
platforms with increasingly many cores. Existing techniques do not scale to hundreds of …

Data processing pipelines normally use lockless Single‐Producer–Single‐Consumer
(SPSC) queues to efficiently decouple their processing threads and achieve high …

In recent years, the number of CPU cores in a multi-core processor keeps increasing. To
leverage the increasing hardware resource, programmers need to develop parallelized …

Buffer sharing based on pipeline parallelism is quite susceptible to inter-core
communication overhead. Existing work on concurrent lock-free (CLF) queue algorithm did …

With the coming of the Internet of things (IoT) era and the development of semiconductor
equipment, multicore processors have begun to be widely used in IoT devices to meet their …