A review on SRAM-based computing in-memory: Circuits, functions, and applications
Z Lin, Z Tong, J Zhang, F Wang, T Xu… - Journal of …, 2022 - iopscience.iop.org
Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it
poses new challenges to system design in terms of computational speed and energy …
poses new challenges to system design in terms of computational speed and energy …
A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications
In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to
reducing power and energy consumption can show high reliability and have the least error …
reducing power and energy consumption can show high reliability and have the least error …
A reconfigurable 4T2R ReRAM computing in-memory macro for efficient edge applications
Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a
promising solution to overcome the von-Neumann bottleneck in conventional computing …
promising solution to overcome the von-Neumann bottleneck in conventional computing …
An energy-efficient hybrid SRAM-based in-memory computing macro for artificial intelligence edge devices
The von Neumann computing architecture faces considerable challenges (eg, high
throughput and improving energy efficiency) in develo** artificial intelligence (AI) edge …
throughput and improving energy efficiency) in develo** artificial intelligence (AI) edge …
BP-SCIM: A reconfigurable 8T SRAM macro for bit-parallel searching and computing in-memory
This work presents BP-SCIM: a reconfigurable 8T static random access memory (SRAM)
macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write …
macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write …
A 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI
This work proposes an static random access memory (SRAM) with column-based split cell-
VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28 …
VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28 …
A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications
Read decoupled SRAM cells were proposed to address the conflicting read and write
requirements in conventional 6 T SRAM cells. However, even read decoupled SRAM cells …
requirements in conventional 6 T SRAM cells. However, even read decoupled SRAM cells …
A 350 mV, 2 MHz, 16-kb SRAM with programmable wordline boosting in the 65 nm CMOS technology
The paper presents an SRAM macro capable of working down to 350ámV with
programmable wordline boosting feature. Wordline boosting allows us to improve the …
programmable wordline boosting feature. Wordline boosting allows us to improve the …
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications
L Lu - IEEE Transactions on Circuits and Systems II: Express …, 2023 - ieeexplore.ieee.org
This brief presents a 10T static random-access memory (SRAM)–computing in memory
(CIM) structure of 32kb macro unit for convolutional neural networks (CNNs). The proposed …
(CIM) structure of 32kb macro unit for convolutional neural networks (CNNs). The proposed …
[CITATION][C] Design of Low Power 15T SRAM Cell using 20nm technology Based on FinFET, CNTFET and GNRFET
DT Lanka, SR Prasad, KS Rao