This paper describes an integrated network-on-chip architecture containing 80 tiles
arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both …

One of the most effective techniques to reduce a processor's power consumption is to
reduce supply voltage. However, reducing voltage in the context of manufacturing-induced …

The 5G era is upon us, ushering in new opportunities for technology innovation across the
computing and connectivity landscape. The advent of the Internet of Things has resulted in …

CMOS-technology scaling has moved to a power-constrained condition regardless of the
application segments. Power management in advanced CMOS technology drives the need …

Over the last 25 years, the use of caches has advanced significantly in mainstream
microprocessors to address the memory wall challenge. As we transformed microprocessors …

In the present time, great emphasis has been given to the design of low-power and high
performance memory circuits. As an SRAM is a critical component in both high-performance …

The bulkiness of current electronic nose (E-Nose) systems severely limits their portability.
This study designed and fabricated an E-Nose signal-processing chip by using TSMC 0.18 …

The variation tolerant assist circuits of an SRAM against process and temperature are
proposed. Passive resistances are introduced to the read assist circuit with replica memory …

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage
operation. A self-write-back sense amplifier realizes cell failure rate improvement by more …

Low power supply operation with leakage power reduction is the prime concern in modern
nano-scale CMOS memory devices. In the present scenario, low leakage memory …