A survey on design approaches to circumvent permanent faults in networks-on-chip
Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …
Application map** onto mesh-based network-on-chip using discrete particle swarm optimization
This paper presents a discrete particle swarm optimization (PSO)-based strategy to map
applications on both 2-D and 3-D mesh-connected Networks-on-Chip. The basic PSO …
applications on both 2-D and 3-D mesh-connected Networks-on-Chip. The basic PSO …
[ΒΙΒΛΙΟ][B] Network-on-chip: the next generation of system-on-chip integration
S Kundu, S Chattopadhyay - 2014 - library.oapen.org
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip:
The Next Generation of System-on-Chip Integration examines the current issues restricting …
The Next Generation of System-on-Chip Integration examines the current issues restricting …
Design-space exploration and optimization of an energy-efficient and reliable 3-D small-world network-on-chip
A 3-D network-on-chip (NoC) enables the design of high performance and low power many-
core chips. Existing 3-D NoCs are inadequate for meeting the ever-increasing performance …
core chips. Existing 3-D NoCs are inadequate for meeting the ever-increasing performance …
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Abstract Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an
auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect …
auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect …
Optimizing 3D NoC design for energy efficiency: A machine learning approach
Three-dimensional (3D) Network-on-Chip (NoC) is an emerging technology that has the
potential to achieve high performance with low power consumption for multicore chips …
potential to achieve high performance with low power consumption for multicore chips …
On the efficacy of through-silicon-via inductors
Through-silicon-vias (TSVs) can potentially be used to implement inductors in 3-D integrated
systems for minimal footprint and large inductance. However, different from conventional 2-D …
systems for minimal footprint and large inductance. However, different from conventional 2-D …
Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip
Reliability is one of the most challenging problems in the context of three-dimensional
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
AFRA: A low cost high performance reliable routing for 3D mesh NoCs
S Akbari, A Shafiee, M Fathy… - 2012 Design, Automation …, 2012 - ieeexplore.ieee.org
Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D
many-core ICs. Such networks have shorter communication hop count, compared to 2D …
many-core ICs. Such networks have shorter communication hop count, compared to 2D …
Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems
During the last few decades, Three-dimensional Network-on-Chips (3D-NoCs) have been
showing their advantages against 2D-NoC architectures. This is thanks to the reduced …
showing their advantages against 2D-NoC architectures. This is thanks to the reduced …