Efficacy of transistor stacking on flip-flop SEU performance at 22-nm FDSOI node
Fully-depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event (SE)
performance compared with comparable bulk technologies. However, upsets are still …
performance compared with comparable bulk technologies. However, upsets are still …
SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node
Compared with bulk technologies, Fully-depleted silicon-on-insulator (FD SOI) technology
nodes show better resistance to single-event upsets. However, additional hardening …
nodes show better resistance to single-event upsets. However, additional hardening …
Charge-steering latch design in 16 nm FinFET technology for improved soft error hardness
B Narasimham, K Chandrasekharan… - … on Nuclear Science, 2016 - ieeexplore.ieee.org
A charge-steering based latch hardening technique with very low performance tradeoff and
significant SEU hardness is presented. Mixed-mode 3D-TCAD simulations are used to …
significant SEU hardness is presented. Mixed-mode 3D-TCAD simulations are used to …
Frequency dependence of heavy-ion-induced single-event responses of flip-flops in a 16-nm bulk FinFET technology
Integrated circuits fabricated at advanced technology nodes are expected to operate in
gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced …
gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced …
Thermal neutron-induced soft-error rates for flip-flop designs in 16-nm bulk FinFET technology
Soft-error rates (SER) of Flip-Flop (FF) designs in a 16-nm bulk FinFET technology are
characterized with thermal neutron, high-energy neutron and alpha particle irradiations …
characterized with thermal neutron, high-energy neutron and alpha particle irradiations …
Power-aware SE analysis of different FF designs at the 14-/16-nm bulk FinFET CMOS technology node
As the minimum feature size on an integrated circuit continues to shrink aggressively toward
deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a …
deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a …
Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages
Single-event (SE) cross-section trends are investigated at near-threshold-voltage (NTV)
supply voltages for conventional D-flip-flop (D-FF) designs with different VT options and …
supply voltages for conventional D-flip-flop (D-FF) designs with different VT options and …
Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology
H Zhang, H Jiang, MR Eaker, KJ Lezon… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
Physical unclonable functions (PUF) have been used to securely authenticate devices in
electronic systems. In this paper, different flip-flop (FF) designs at a 14/16-nm bulk FinFET …
electronic systems. In this paper, different flip-flop (FF) designs at a 14/16-nm bulk FinFET …
Single Event Transient Filtering Transfer Gate: A Layout-Aware Simulation Study
K Takeuchi, K Sakamoto, T Sakamoto… - 2023 23rd European …, 2023 - ieeexplore.ieee.org
This paper proposes the single event transient filtering transfer gate (SIFT). A layout-aware
simulation of the technology computer-aided design (TCAD) was performed to evaluate the …
simulation of the technology computer-aided design (TCAD) was performed to evaluate the …
Design of a New SEU-tolerant SRAM Cell Structure
Z CHANG, QIN Jiajun, Z Lei, S Chunxiao, LI Li, AN Qi - 原子核物理评论, 2023 - npr.ac.cn
In accelerator particle physics experiments, it is a development trend to realize the functions
of analog signal processing and digitization at the front end of readout electronics based on …
of analog signal processing and digitization at the front end of readout electronics based on …