[PDF][PDF] 区块链共识机制研究综述

刘懿中, 刘建伟, 张宗洋, 徐同阁, 喻辉 - 密码学报, 2019 - jcr.cacrnet.org.cn
自比特币被提出以来, 数字货币开启了新的时代, 而其背后的区块链技术也逐渐受到各界人士的
重视. 共识机制作为区块链技术的核心, 决定了区块链的安全性, 可扩展性和去中心化程度等许多 …

Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding

D **ang, X Wen, LT Wang - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on
weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture …

Test point insertion based on path tracing

NA Touba, EJ McCluskey - Proceedings of 14th VLSI Test …, 1996 - ieeexplore.ieee.org
This paper presents an innovative method for inserting test points in the circuit-under-test to
obtain complete fault coverage for a specified set of test patterns. Rather than using …

Special session: Survey of test point insertion for logic built-in self-test

Y Sun, SK Millican, VD Agrawal - 2020 IEEE 38th VLSI Test …, 2020 - ieeexplore.ieee.org
This article surveys test point (TP) architectures and test point insertion (TPI) methods for
increasing pseudo-random and logic built-in self-test (LBIST) fault coverage. We present a …

Weighted pseudorandom hybrid BIST

A Jas, CV Krishna, NA Touba - IEEE Transactions on Very …, 2004 - ieeexplore.ieee.org
This paper presents a new test data-compression scheme that is a hybrid approach between
external testing and built-in self-test (BIST). The proposed approach is based on weighted …

Low hardware overhead scan based 3-weight weighted random BIST

S Wang - Proceedings International Test Conference 2001 (Cat …, 2001 - ieeexplore.ieee.org
Two noble scan based BIST architectures, namely parallel fixing and serial fixing BIST,
which can be implemented at very low hardware cost even for random pattern resistant …

A BIST TPG for low power dissipation and high fault coverage

S Wang - IEEE transactions on very large scale integration …, 2007 - ieeexplore.ieee.org
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based
built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during …

Generation of low power dissipation and high fault coverage patterns for scan-based BIST

S Wang - Proceedings. International Test Conference, 2002 - ieeexplore.ieee.org
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based
BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault …

Low-power programmable PRPG with test compression capabilities

M Filipek, G Mrugalski, N Mukherjee… - … Transactions on Very …, 2014 - ieeexplore.ieee.org
This paper describes a low-power (LP) programmable generator capable of producing
pseudorandom test patterns with desired toggling levels and enhanced fault coverage …

BIST for systems-on-a-chip

HJ Wunderlich - Integration, 1998 - Elsevier
An increasing part of microelectronic systems is implemented on the basis of predesigned
and preverified modules, so-called cores, which are reused in many instances. Core …