Indium-tin-oxide for high-performance electro-optic modulation

Z Ma, Z Li, K Liu, C Ye, VJ Sorger - Nanophotonics, 2015 - degruyter.com
Advances in opto-electronics are often led by discovery and development of materials
featuring unique properties. Recently, the material class of transparent conductive oxides …

A survey on optical network-on-chip architectures

S Werner, J Navaridas, M Luján - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
Optical on-chip data transmission enabled by silicon photonics (SiP) is widely considered a
key technology to overcome the bandwidth and energy limitations of electrical interconnects …

Photonic multiply-accumulate operations for neural networks

MA Nahmias, TF De Lima, AN Tait… - IEEE Journal of …, 2019 - ieeexplore.ieee.org
It has long been known that photonic communication can alleviate the data movement
bottlenecks that plague conventional microelectronic processors. More recently, there has …

Enabling interposer-based disintegration of multi-core processors

A Kannan, NE Jerger, GH Loh - … of the 48th international symposium on …, 2015 - dl.acm.org
Silicon interposers enable the integration of multiple stacks of in-package memory to provide
higher bandwidth or lower energy for memory accesses. Once the interposer has been paid …

SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip

HMG Wassel, Y Gao, JK Oberg, T Huffmire… - ACM SIGARCH …, 2013 - dl.acm.org
As multicore processors find increasing adoption in domains such as aerospace and
medical devices where failures have the potential to be catastrophic, strong performance …

Crono: A benchmark suite for multithreaded graph algorithms executing on futuristic multicores

M Ahmad, F Hijaz, Q Shi, O Khan - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
Algorithms operating on a graph setting are known to be highly irregular and unstructured.
This leads to workload imbalance and data locality challenge when these algorithms are …

Dynamic voltage and frequency scaling in NoCs with supervised and reinforcement learning techniques

Q Fettes, M Clark, R Bunescu… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Network-on-Chips (NoCs) are the de facto choice for designing the interconnect fabric in
multicore chips due to their regularity, efficiency, simplicity, and scalability. However, NoC …

NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?

NE Jerger, A Kannan, Z Li… - 2014 47th Annual IEEE …, 2014 - ieeexplore.ieee.org
Silicon interposer technology (" 2.5 D" stacking) enables the integration of multiple memory
stacks with a processor chip, thereby greatly increasing in-package memory capacity while …

Breaking the on-chip latency barrier using SMART

T Krishna, CHO Chen, WC Kwon… - 2013 IEEE 19th …, 2013 - ieeexplore.ieee.org
As the number of on-chip cores increases, scalable on-chip topologies such as meshes
inevitably add multiple hops in each network traversal. The best we can do right now is to …

Power punch: Towards non-blocking power-gating of noc routers

L Chen, D Zhu, M Pedram… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
As chip designs penetrate further into the dark silicon era, innovative techniques are much
needed to power off idle or under-utilized system components while having minimal impact …