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Logic circuit simulator and logic simulation method having reduced number of simulation events
TW Ku, WK Chia, DR Shieh - US Patent 5,384,720, 1995 - Google Patents
[57] ABSTRACT A logic simulation system and method reduces the num ber of events to be
simulated. The simulator receives a user speci? ed circuit netlist denoting a speci? ed logic …
simulated. The simulator receives a user speci? ed circuit netlist denoting a speci? ed logic …
Reconfigurable machine and its application to logic diagnosis
Suganuma, Murata, Nakata, Nagata… - 1992 IEEE/ACM …, 1992 - ieeexplore.ieee.org
It is pointed out that in the reconfigurable machine (RM) highly flexible architecture
combining field-programmable gate arrays (FPGAs) with RAMs supports a wide range of …
combining field-programmable gate arrays (FPGAs) with RAMs supports a wide range of …
Reconfigurable machine and its application to logic simulation
N TOMITA, N Suganuma, K Hirano - IEICE TRANSACTIONS on …, 1993 - search.ieice.org
Logic Simulation Page 1 IEICE TRANS. FUNDAMENTALS, VOL. E76-A, NO. 10 OCTOBER
1993 1705 ||PAPER Special Section on VLSI Design and CAD Algorithms Reconfigurable …
1993 1705 ||PAPER Special Section on VLSI Design and CAD Algorithms Reconfigurable …
[КНИГА][B] Parallel algorithms for placement and routing in VLSI design
RJ Brouwer - 1991 - search.proquest.com
The computational requirements for high quality synthesis, analysis, and verification of VLSI
designs have rapidly increased with the fast growing complexity of these designs. Past …
designs have rapidly increased with the fast growing complexity of these designs. Past …
Reconfigurable Machine and Its Application to Logic Diagnosis
S Nagata, M Tomita, K Hirano - computer.org
It is pointed out that in the reconfigurable machine (RM) highly flexible architecture
combining field-programmable gate arrays (FPGAs) with RAMs supports a wide range of …
combining field-programmable gate arrays (FPGAs) with RAMs supports a wide range of …
[ОПИСАНИЕ][C] Parallel demand-driven distributed-time logic circuit simulation
CA Cooper - 1995 - unsworks.unsw.edu.au
ABSTRACT Parallel Discrete Event Simulation algorithms (PDES) are gaining in popularity
as a means of improving performance in VLSI chip/circuit design and testing. Although the …
as a means of improving performance in VLSI chip/circuit design and testing. Although the …