Recent developments in high-level synthesis

YL Lin - ACM Transactions on Design Automation of Electronic …, 1997 - dl.acm.org
We survey recent developments in high level synthesis technology for VLSI design. The
need for higher-level design automation tools are discussed first. We then describe some …

[BOK][B] Handbook of bioinspired algorithms and applications

S Olariu, AY Zomaya - 2005 - books.google.com
This authoritative handbook reveals the connections between bioinspired techniques and
the development of solutions to problems that arise in diverse problem domains. It provides …

An algorithm for hardware/software partitioning using mixed integer linear programming

R Niemann, P Marwedel - Design Automation for Embedded Systems, 1997 - Springer
One of the key problems in hardware/software codesign is hardware/software partitioning.
This paper describes a new approach to hardware/software partitioning using integer …

Hardware/software partitioning using integer programming

R Niemann, P Marwedel - Proceedings ED&TC European …, 1996 - ieeexplore.ieee.org
One of the key problems in hardware/software codesign is hardware/software partitioning.
This paper describes a new approach to hardware/software partitioning using integer …

[BOK][B] Code optimization techniques for embedded processors: Methods, algorithms, and tools

R Leupers - 2013 - books.google.com
The building blocks of today's and future embedded systems are complex intellectual
property components, or cores, many of which are programmable processors. Traditionally …

Bitwidth cognizant architecture synthesis of custom hardware accelerators

S Mahlke, R Ravindran, M Schlansker… - … on Computer-Aided …, 2001 - ieeexplore.ieee.org
Program-in chip-out (PICO) is a system for automatically synthesizing embedded hardware
accelerators from loop nests specified in the C programming language. A key issue …

Performance optimization using template map** for datapath-intensive high-level synthesis

MR Corazao, MA Khalaf, LM Guerra… - … on Computer-Aided …, 1996 - ieeexplore.ieee.org
This paper introduces a new approach to performance-driven template map** for high-
level synthesis. Template map**, the process of map** high-level algorithmic …

[BOK][B] Synthesis and optimization of DSP algorithms

G Constantinides, PYK Cheung, W Luk - 2007 - books.google.com
Synthesis and Optimization of DSP Algorithms describes approaches taken to synthesising
structural hardware descriptions of digital circuits from high-level descriptions of Digital …

Time-constrained code compaction for DSPs

R Leupers, P Marwedel - … of the 8th international symposium on System …, 1995 - dl.acm.org
DSP algorithms are, in most cases, subject to hard real-time constraints. In the case of
programmable DSPs, meeting those constraints must be ensured by appropriate code …

Optimal temporal partitioning and synthesis for reconfigurable architectures

M Kaul, R Vemuri - … Design, Automation and Test in Europe, 1998 - ieeexplore.ieee.org
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning
and high-level synthesis from behavioral specifications destined to be implemented on …