The economic and social demand for ubiquitous and multifaceted electronic systems-in
combination with the unprecedented opportunities provided by the integration of various …

The test scheduling problem for equal length and unequal length tests for VLSI circuits using
built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is …

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small
likelihood of error escape (aliasing) is described. For test generation, the scheme uses the …

Focuses on the design and production of integrated circuits specifically designed for a
particular application from original equipment manufacturers. The book outlines silicon and …

The authors argue that because of misconceptions and myths about the cost of test, many
devices and systems are inadequately tested. Focusing on application-specific integrated …

A novel scheme to design built-in self-test programmable logic arrays (PLAs) implemented
with CMOS technology is described, which is attractive for large arrays. These PLAs can …

This paper presents the design of a programmable logic array with redundancy. The design
allows for the repair of a defective chip by including the redundancy circuits to a …

Programmable logic arrays (PLA's) are extensively used to realize area efficient
combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test …

When designing fault-tolerant systems including programmable logic arrays (PLAs), the
various aspects of these circuits concerning fault diagnosis have to be taken into account …

The authors analyze two D flip-flops (DFF's) generally considered to be the fastest (and most
widely used), and compare their speed performance and their robustness against clock …