Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for
matrix multiplication and accumulation to be performed within the memory array. A unit …

A hardware device and method for performing a multiply-accumulate operation are
described. The device includes inputs lines, weight cells and output lines. The input lines …

Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for
matrix multiplication and accumulation to be performed within the memory array. A unit …

LLP (57) ABSTRACT Use of a NAND array architecture to realize a binary neural network
(BNN) allows for matrix multiplication and accu mulation to be performed within the memory …

An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a
second DAC, a plural ity of non-volatile memory (NVM) weight arrays, one or more analog-to …

Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix
multiplication and accu mulation to be performed within the memory array. A unit synapse for …

US11625586B2 - Realization of neural networks with ternary inputs and ternary weights in
NAND memory arrays - Google Patents US11625586B2 - Realization of neural networks with …

US11657259B2 - Kernel transformation techniques to reduce power consumption of binary
input, binary weight in-memory convolutional neural network inference engine - Google …

Techniques are presented for accelerating in-memory matrix multiplication operations for a
convolution neural network (CNN) inference in which the weights of a filter are stored in the …

(57) ABSTRACT A method for accelerating a convolution of a kernel matrix over an input
matrix for computation of an output matrix using in-memory computation involves storing in …